Aditya Dayal M. Tech, VLSI Design ITM University, Gwalior

 The Advanced Microcontroller Bus Architecture (AMBA) is used as the on-chip bus in system-on-a- chip(SoC) designs.  The scope of AMBA has gone far beyond microcontroller devices, and is now widely used on a range of ASIC and SoC parts including applications processors used in modern portable mobile devices like smartphones.  The AMBA protocol is an on-chip interconnect specification for the connection and management of functional blocks in a System-on-Chip (SoC).  It facilitates development of multi-processor designs with large numbers of controllers and peripherals.

APB ASB AHB AXI Time Performance ARM Protocols-history

 AMBA was introduced by ARM Ltd in  The first AMBA buses were Advanced System Bus (ASB) and Advanced Peripheral Bus (APB).  In its 2nd version, AMBA 2, ARM added AMBA High-performance Bus (AHB) that is a single clock-edge protocol.  In 2003, ARM introduced the 3rd generation, AMBA 3, including AXI to reach even higher performance interconnect and the Advanced Trace Bus (ATB) as part of the Core-Sight on-chip debug and trace solution.  THIS enables software and hardware developers to identify real-time software or hardware defects and quickly resolve them, ensuring higher productivity and lower risk developments.  IN 2010,ARM introduced the 4 th generation, AMBA 4 including AMBA 4 AXI4,AXI4-Lite, and AXI4-Stream Protocol.

o AHB (Advanced High-performance bus) Highest performance bus in AMBA family before AXI. The AMBA AHB is for high-performance, high clock frequency system modules. The AHB acts as the high-performance system backbone bus. AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces. Suitable for medium complexity. o AHB –Lite Subset of the full AHB specification. Intended preferably for use in designs where only a single master is used.

o APB (Advanced Peripheral Bus)  AMBA APB is optimized for minimal power consumption and reduced interface complexity to support peripherals such as timers, interrupt controllers, UARTs, I/O ports, etc.  Connected to the system bus via a bridge, helps reduce system power consumption  Easy to interface to, with little logic involved and a few corner cases to validate. o AXI (Advanced Extensible Bus)  Highly flexible.  Higher performance interconnect.

AMBA BUS ARCHITECTURE AMBA BUS ARCHITECTURE High- bandwidth External memory Interface High performance ARM processor High bandwidth on_-chip RAM AHB or AXI AHB to APB Bridge or AXI to APB bridge APB DMA bus master BRIDGEBRIDGE UAR T Timer Keypa d PIO  Application Type o Serves as a framework for SoC designs. System-on-a-chip (SoC) designs. On-chip bus for arm processors.

 Mobile segment o Feature phone o Voice phone o PDAs o Portable Audio o Smart phone o Portable Media o Digital Camera  Home segment o Set Top Box o DTV/HDTV o DSC/DVC o DVD o Tethered Gaming o Portable Gaming

AMBA AHBAMBA APB Feature  High performance  Pipelined operation  Multiple bus masters  Burst transfers  Single clock edge operation  Wider data bus configuration  Non tri state implementation  Low power  Latched address and control  Simple interface  Suitable for many peripherals  Single clock edge operation Components  AHB master  AHB slave  AHB multiplexer  AHB decoder  APB bridge (slave on AHB or AXI)  APB slave

Signal NameSize (bits)Description PCLK1The bus clock times all bus transfers. All signal timings are related to the rising edge of PCLK. PRESETn1The bus reset signal is active LOW and resets the system and the bus. This is active LOW.

Signal NameSizeDescription PADDAR32 This is the APB address bus. It can be up to 32 bits wide and is driven by the peripheral bus bridge unit. PSELx 1 The APB bridge unit generates this signal to each peripheral bus slave. It indicates that the slave device is selected and that a data transfer is required. There is a PSELx signal for each slave. PENABLE 1 This signal indicates the second and subsequent cycles of an APB transfer. PWRITE 1 This signal indicates an APB write access when HIGH and an APB read access when LOW. PWDATA32 This bus is driven by the peripheral bus bridge unit during write cycles when PWRITE is High.

Signal nameSizeDescription PREADY 1 The slave uses this signal to extend an APB transfer. PRDATA 32 The selected slave drives this bus during read cycles when PWRITE is Low. PSLVERR 1 This signal indicates a transfer failure. APB peripherals are not required to support the PSLVERR. This is true for both existing and new APB peripheral designs. Where a peripheral does not include this pin then the appropriate input to the APB bridge is tied LOW.

 The state machine operates through the following states: o IDLE : This is the default state of the APB. o SETUP : When a transfer is required the bus moves into the SETUP state, where the appropriate select signal, PSELx, is asserted. The bus only remains in the SETUP state for one clock cycle and always moves to the ACCESS state on the next rising edge of the clock. o ACCESS : The enable signal, PENABLE, is asserted in the ACCESS state. The address, write, select, and write data signals must remain stable during the transition from the SETUP to ACCESS state. Exit from the ACCESS state is controlled by the PREADY signal from the slave:  If PREADY is held LOW by the slave then the peripheral bus remains in the ACCESS state.  If PREADY is driven HIGH by the slave then the ACCESS state is exited and the bus returns to the IDLE state if no more transfers are required. Alternatively, the bus moves directly to the SETUP state if another transfer follows.