INSIDE – Update meeting PET DAQ 24 March 2014. Refresh from the last meetings Objectives of the PET DAQ – Provide a full in-beam (full-beam) PET system.

Slides:



Advertisements
Similar presentations
L. Greiner 1HFT PXL LBNL F2F – March 14, 2012 STAR HFT The STAR-PXL sensor and electronics Progress report for F2F.
Advertisements

Vincent Boudry Franck Gastaldi Antoine Matthieu David Decotigny CALICE meeting 19 feb Kyungpook Nat'l U., Daegu, Korea Status of the Data Concentrator.
E-link IP for FE ASICs VFAT3/GdSP ASIC design meeting 19/07/2011.
 Electronics for the profiler (Michela e Adalberto)  Profiler: development of an evaluation board for the test (Matteo)  Design of the FE-ASIC (Cristoforo)
28 August 2002Paul Dauncey1 Readout electronics for the CALICE ECAL and tile HCAL Paul Dauncey Imperial College, University of London, UK For the CALICE-UK.
Uli Schäfer 1 JEM: Status and plans JEM1.2 Status Test results Plans.
P09311: Interface for Multi-Purpose Driver/Data Acquisition System Adam Van FleetProject Leader, EE DAQ Hardware Development David HoweElectrical Engineer.
2 Outline Digital music The power of FPGA The “DigitalSynth” project –Hardware –Software Conclusion Demo.
PROBE CARD INTEGRATION IN pALPIDEfs TEST SYSTEM ALICE | ITS-MFT Mini-Week | | Markus Keil.
TE/MPE/EE J. Mourao T/MPE/EE 1 November 2012 LHC Machine Local protection Redundant Power supply (DQLPUR) - Review.
Upgrade developments in Clermont-Ferrand Romeo Bonnefoy and François Vazeille Tilecal upgrade meeting (CERN, 13 June 2014) ● Handling tools ● Deported.
Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France Calorimeter upgrade meeting Olivier Duarte Upgrade calo FE review Comments : Digital.
5 Feb 2002Alternative Ideas for the CALICE Backend System 1 Alternative Ideas for the CALICE Back-End System Matthew Warren and Gordon Crone University.
Larg. Week, April 2002, Electronics Meeting1 Progress Report On Electronics Activities in Paris Bertrand Laforge LPNHE Paris CNRS/IN2P3 – Universités Paris.
Saverio Minutoli INFN Genova 1 T1 Electronic status Electronic items involved: Anode Front End Card Cathode Front End Card Read-Out Control card Slow Control.
Electronics for PS and LHC transformers Grzegorz Kasprowicz Supervisor: David Belohrad AB-BDI-PI Technical student report.
Multimedia & Communications ATMEL Bluetooth Background information on Bluetooth technology ATMEL implementation of Bluetooth spec.
BepiColombo/MMO/PWI/SORBET PWI meeting - Kanazawa 24/03/2006M.Dekkali MMO PWI Meeting Kanazawa University 24 th March 2006.
In-Beam PET Status Report -- TPS. 2 TPS project PET monitoring prototype 2D view of the FOV coverage of the 4+4 modules Use of 4 modules vs. 4 modules.
HEP UCL Cambridge University Imperial College London University of Manchester Royal Holloway, University of London University College London Matthew Warren,
Motherboard (Main board)
SODA: Synchronization Of Data Acquisition I.Konorov  Requirements  Architecture  System components  Performance  Conclusions and outlook PANDA FE-DAQ.
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
Wing LDA CALICE Collaboration Meeting DESY Hamburg, 21. March 2013 André Welker Lennart Adam, Bruno Bauss, Volker Büscher, Reinhold Degele, Karl Heinz.
AIDA FEE64 development report August 2010 Progress after Texas CAD work Manufacturing 25th August
1 DAQ for FVTX detector Implementation Mark Prokop Los Alamos National Laboratory.
David Bailey University of Manchester. Overview Aim to develop a generic system –Maximise use of off-the-shelf commercial components Reduce as far as.
Gueorgui ANTCHEVPrague 3-7 September The TOTEM Front End Driver, its Components and Applications in the TOTEM Experiment G. Antchev a, b, P. Aspell.
Fullbeam DAQ board on PET system Eleftheria Kostara (INFN of Pisa, University of Siena ) Supervisors: F. Palla, M.G. Bisogni (University of Pisa) Technical.
CCD Cameras with USB2.0 & Gigabit interfaces for the Pi of The Sky Project Grzegorz Kasprowicz Piotr Sitek PERG In cooperation with Soltan Institute.
FVTX Electronics (WBS 1.5.2, 1.5.3) Sergey Butsyk University of New Mexico Sergey Butsyk DOE FVTX review
24/03/2010 TDAQ WG - CERN 1 LKr L0 trigger status report V. Bonaiuto, G. Carboni, L. Cesaroni, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti,
07-Jan-2010 Jornadas LIP 2010, Braga JC. Da SILVA Electronics systems for the ClearPEM-Sonic scanner José C. DA SILVA, LIP-Lisbon Tagus LIP Group * *J.C.Silva,
P09311: FPGA Based Multi-Purpose Driver / Data Acquisition System Sponsor: Dr. Marcin Lukowiak Team MemberDisciplineRole Adam Van FleetEEProject Manager/Documentation.
SRS Activities at IFIN-HH: VMM2 Hybrid, FECv6 Firmware, High- Density Optical ATCA-SRS Mezzanine Sorin Martoiu, Michele Renda, Paul Vartolomei (IFIN-HH.
Barcelona 1 Development of new technologies for accelerators and detectors for the Future Colliders in Particle Physics URL.
FVTX Electronics (WBS 1.5.2, 1.5.3) Sergey Butsyk University of New Mexico Sergey Butsyk DOE FVTX review
Status & development of the software for CALICE-DAQ Tao Wu On behalf of UK Collaboration.
JRA-1 Meeting, Jan 25th 2007 A. Cotta Ramusino, INFN Ferrara 1 EUDRB: A VME-64x based DAQ card for MAPS sensors. STATUS REPORT.
1 Preparation to test the Versatile Link in a point to point configuration 1.Versatile Link WP 1.1: test the Versatile Link in a point to point (p2p) configuration.
Peter LICHARD CERN (NA62)1 NA62 Straw tracker electronics Study of different readout schemes Readout electronics frontend backend Plans.
16 February 2011Ian Brawn1 The High Speed Demonstrator and Slice Demonstrator Programme The Proposed High-Speed Demonstrator –Overview –Design Methodology.
M.Matveev Rice University March 20, 2002 EMU Muon Port Card Project.
Julie Prast, Calice Electronics Meeting at LAL, June 2008 Status of the DHCAL DIF Detector InterFace Board Sébastien Cap, Julie Prast, Guillaume Vouters.
Standard electronics for CLIC module. Sébastien Vilalte CTC
09/09/2010 TDAQ WG - Louvain 1 LKr L0 trigger status report V. Bonaiuto, A. Fucci, G. Paoluzzi, A. Salamon, G. Salina, E. Santovetti, F. Sargeni, F. Scarfi’
L1Topo post review Uli Schäfer 1 Observations, options, effort, plans Uli.
Update on works with SiPMs at Pisa Matteo Morrocchi.
X SuperB Workshop - SLAC Oct 06 to Oct 09, 2009 A.Cotta Ramusino, INFN Ferrara 1 SuperB IFR: outline of the IFR prototype electronics A.C.R
DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.
News from the 1m 2 GRPC SDHCAL collection of slides from : Ch.Combaret, I.L, H.Mathez, J.Prast, N.Seguin, W.Tromeur, G.Vouters and many others.
System on a Programmable Chip (System on a Reprogrammable Chip)
29/05/09A. Salamon – TDAQ WG - CERN1 LKr calorimeter L0 trigger V. Bonaiuto, L. Cesaroni, A. Fucci, A. Salamon, G. Salina, F. Sargeni.
EDUSAFE FINAL CONFERENCE June, 2016
The Data Handling Hybrid
Programmable Hardware: Hardware or Software?
Pid session TDC-based electronics for the CRT
INSIDE in-beam PET system assembly and test at INFN Torino
Production Firmware - status Components TOTFED - status
INSIDE – Update meeting
Update on the development of the PET data acquisition system
Update on CSC Endcap Muon Port Card
Electronics, Trigger and DAQ for SuperB
Upgrade of the CSC Endcap Muon Port Card and Optical Links to CSCTF
PADME L0 Trigger Processor
The Complete Solution for Cost-Effective PCI & CompactPCI Implementations 1.
CMS EMU TRIGGER ELECTRONICS
Pi Logic Controller Teresa Núñez DESY Photon Science
Greg Bell Business Development Mgr Industrial & Security Markets
ECE 4006-B GIGABIT ETHERNET GROUP #7 Update Presentation #10
Presentation transcript:

INSIDE – Update meeting PET DAQ 24 March 2014

Refresh from the last meetings Objectives of the PET DAQ – Provide a full in-beam (full-beam) PET system able to sustain annihilation and prompt photon rates during the beam irradiation – Instant single rates in the microsecond range are currently unknown – As a first guess we take 30 kHZ/cm 2 as the desired maximum sustainable single rate ( ∼ 6× with respect to DoPET) – Provide a dedicated PET scanner with a coincidence window (CW) of 500 ps

Data acquisition flow Each SiPM/ASIC pair can handle single rates at 180 kHZ The 5 cm x 5 cm module will acquire at 720 kHZ Data collected by two FPGAs – TX, coupled to the ASIC – RX, plugged on the mainboard Data packet is 10 B The expected module output bandwidth is 7.2 MB/s

Updates

Motherboard HW development Functional design ✔ Schematic design ✔ Mechanical design ✔ PCB design (in progress) Construction and assembly ✖ Initial delivery 12/2013, expected delivery 4/2013

Motherboard FW development Functional architecture design ✔ USB interface (imported from DoPET) RX interface (under development) Coincidence sorter and processor ✖ Expected first version delivery 12/2014 (depending on HW status)

Motherboard SW development Largely imported from DoPET Server/client architecture, suitable for multi- modal integration (same as for IrisPET) No specific developments are being made at the moment

RX board development Initial FW development with the SoCKit board Cyclone V SX 5CSXFC6D6 FPGA Equipped with ARM processor

RX board development Customizing and producing a new board based on the same technology The HSMC connector is kept to communicate with the TX board + Motherboard connector + Motherboard connector

RX FW board development The RX FW architecture is relatively simple – SPI slave component – FIFO buffers – SERDES

RX SW board development The RX does not require SW development However, the ARM processors offer simple and flexible solutions to processing problems This is a new aspect of SoC FPGA that is under investigation