SOC & VLSI PROCESSOR Sumana Kumar 04/26/2011

SOC & VLSI Project : Network on chip Team : Processor team Group : Sumana Kumar Harold Yu Fu Lin Guidance : Dr. Levitan Dr. Jones

SOC & VLSI: Network on chip Block diagram from kona.ee.pitt.edu/socvlsi

SOC & VLSI: Network on chip Introduction : This project involved the development of a multi-processor network My team was involved in : 1. Developing a buffer 2. Compiling and simulating the ARM cortexM0 processor 3. Generating the ram.bin files for the memory

SOC & VLSI: Network on chip Synthesis of the Cortexm0 processor DC synthesis was performed Synthesis successful at 130MHz Fig : Screen shot showing the slack is 0

SOC & VLSI: Network on chip Place and route of cortexm0 Encounter tool was used Fig : screenshot showing the post route timing report. No errors and no violations encontered

SOC & VLSI Size : 536.9um * 541.3um

SOC & VLSI: Network on chip Modelsim was used for simulating and testing the Cortexmo processor Post PR simulation runs at 100 MHz

SOC & VLSI: Network on chip ARM compiler This was used to generate the ram.bin files required for the memory Hello world program was first first converted into a ram.bin file from a.c file This was modified to read ‘Hell word’ to test and prove the working of the generated ram.bin files

SOC & VLSI: Network on chip

SOC & VLSI: Network on Chip Gain: A clear understanding of high level and low level design Usage of DC, Modelsim, Encounter and the ARM compiler Concepts incolved in the processor and memory developments

SOC & VLSI THANK YOU

SOC & VLSI