ULTRALEV: Ultra-Low-Energy Video Sensor Networks for IoT ($700B market) Technology Research Center University of Turku Finland.

Slides:



Advertisements
Similar presentations
DSPs Vs General Purpose Microprocessors
Advertisements

Energy Efficiency, Arithmetics and Design Effort on FPGAs Case study: Reconfigurable Miniature Sensor Nodes for Condition Monitoring Teemu Nyländen, Jani.
Keeping Hot Chips Cool Ruchir Puri, Leon Stok, Subhrajit Bhattacharya IBM T.J. Watson Research Center Yorktown Heights, NY Circuits R-US.
Evaluating an Adaptive Framework For Energy Management in Processor- In-Memory Chips Michael Huang, Jose Renau, Seung-Moon Yoo, Josep Torrellas.
In God We Trust Class presentation for the course: “Custom Implementation of DSP systems” Presented by: Mohammad Haji Seyed Javadi May 2013 Instructor:
Topic 3: Sensor Networks and RFIDs Part 2 Instructor: Randall Berry Northwestern University MITP 491: Selected Topics.
Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick Palmer University of British Columbia (UBC) Vancouver, BC, Canada A 3GHz Switching.
Platform-based Design 5KK70 TU/e 2009 Henk Corporaal Bart Mesman.
L27:Lower Power Algorithm for Multimedia Systems 성균관대학교 조 준 동
Embedded Computer Architecture 5KK73 TU/e Henk Corporaal
Chapter 1 CSF 2009 Computer Performance. Defining Performance Which airplane has the best performance? Chapter 1 — Computer Abstractions and Technology.
Introduction.
UC Berkeley B. Nikolić Architecture choices MAC Unit Addr Gen  P Prog Mem Embedded Processor (lpArm) Direct Mapped Hardware Embedded FPGA DSP (e.g. TI.
Improving the Efficiency of Memory Partitioning by Address Clustering Alberto MaciiEnrico MaciiMassimo Poncino Proceedings of the Design,Automation and.
A Programmable Coprocessor Architecture for Wireless Applications Yuan Lin, Nadav Baron, Hyunseok Lee, Scott Mahlke, Trevor Mudge Advance Computer Architecture.
Micro-Architecture Techniques for Sensor Network Processors Amir Javidi EECS 598 Feb 25, 2010.
Climate Machine Update David Donofrio RAMP Retreat 8/20/2008.
Processor Frequency Setting for Energy Minimization of Streaming Multimedia Application by A. Acquaviva, L. Benini, and B. Riccò, in Proc. 9th Internation.
RF Wakeup Sensor – On-Demand Wakeup for Zero Idle Listening and Zero Sleep Delay.
IVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor Video analysis technology –Healthcare, HMI, surveillance,
Timepix2 power pulsing and future developments X. Llopart 17 th March 2011.
Institute of Electronics, National Chiao Tung University VLSI Signal Processing Lab A 242mW, 10mm2 H.264/AVC High Profile Encoder H.264 High Profile Encoder.
Robust Low Power VLSI R obust L ow P ower VLSI Finding the Optimal Switch Box Topology for an FPGA Interconnect Seyi Ayorinde Pooja Paul Chaudhury.
6.893: Advanced VLSI Computer Architecture, September 28, 2000, Lecture 4, Slide 1. © Krste Asanovic Krste Asanovic
Real time DSP Professors: Eng. Julian Bruno Eng. Mariano Llamedo Soria.
Word-Size Optimization for Low Energy, Variable Workload Sub-threshold Systems Sudhanshu Khanna, Anurag Nigam ECE 632 – Fall 2008 University of Virginia.
DRRA Dynamically Reconfigurable Resource Array
Low Power Wireless Design Dr. Ahmad Bahai National Semiconductor.
D. Daly, D. Finchelstein, N. Ickes, N. Verma, A. Chandrakasan An Ultra Low Power Wireless Micro-Sensor Node ADCADCDSPDSPRadioRadio 8/12-bit SAR architecture.
Trigger design engineering tools. Data flow analysis Data flow analysis through the entire Trigger Processor allow us to refine the optimal architecture.
Low-Power Wireless Sensor Networks
Real-Time HD Harmonic Inc. Real Time, Single Chip High Definition Video Encoder! December 22, 2004.
Sogang University Advanced Computing System Chap 1. Computer Architecture Hyuk-Jun Lee, PhD Dept. of Computer Science and Engineering Sogang University.
To be smart or not to be? Siva Subramanian Polaris R&D Lab, RTP Tal Lavian OPENET Lab, Santa Clara.
C OMPUTER O RGANIZATION AND D ESIGN The Hardware/Software Interface 5 th Edition Chapter 1 Computer Abstractions and Technology Sections 1.5 – 1.11.
SHA-3 Candidate Evaluation 1. FPGA Benchmarking - Phase Round-2 SHA-3 Candidates implemented by 33 graduate students following the same design.
ASIP Architecture for Future Wireless Systems: Flexibility and Customization Joseph Cavallaro and Predrag Radosavljevic Rice University Center for Multimedia.
Power Management for Nanopower Sensor Applications Michael Seeman EE 241 Final Project Spring 2005 UC Berkeley.
R2D2 team R2D2 team Reconfigurable and Retargetable Digital Devices  Application domains Mobile telecommunications  WCDMA/UMTS (Wideband Code Division.
Embedded Systems Design: A Unified Hardware/Software Introduction 1 Chapter 3 General-Purpose Processors: Software.
Astronomical Institute University of Bern 31th IADC Meeting, April , 2013, ESOC, Darmstadt, Germany Improved Space Object Observation Techniques.
˜ SuperHeterodyne Rx ECE 4710: Lecture #18 fc + fLO fc – fLO -fc + fLO
Chapter 1 Introduction. Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2002 Chapter 1, Slide 2 Learning Objectives  Why process signals.
ULPVIS: Ultra-Low Power Video Sensor Networks for IoT ($700B market)
Jason Li Jeremy Fowers 1. Speedups and Energy Reductions From Mapping DSP Applications on an Embedded Reconfigurable System Michalis D. Galanis, Gregory.
Practical Strategies for Power-Efficient Computing Technologies Karim Al-Sheraidah December 8 th 2011.
Embedded System. What is an Embedded System? Computing systems embedded within electronic devices Hard to define – Nearly any computing system other than.
Analysis of Cache Tuner Architectural Layouts for Multicore Embedded Systems + Also Affiliated with NSF Center for High- Performance Reconfigurable Computing.
CS 546: Intelligent Embedded Systems Gaurav S. Sukhatme Robotic Embedded Systems Lab Center for Robotics and Embedded Systems Computer Science Department.
ARM offers a broad range of processor cores to address a wide variety of applications while delivering optimum performance, power consumption and system.
Sean Mathews, Christopher Kiser, Haoxiang Chen. Processor Design Tradeoffs: Instruction Set Design Support useful functions while implementing as efficiently.
Adaptive Sleep Scheduling for Energy-efficient Movement-predicted Wireless Communication David K. Y. Yau Purdue University Department of Computer Science.
Patricia Gonzalez Divya Akella VLSI Class Project.
Lx: A Technology Platform for Customizable VLIW Embedded Processing.
Masaya Miyahara, James Lin, Kei Yoshihara and Akira Matsuzawa Tokyo Institute of Technology, Japan A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC.
Seok-jae, Lee VLSI Signal Processing Lab. Korea University
A 1.2V 26mW Configurable Multiuser Mobile MIMO-OFDM/-OFDMA Baseband Processor Motivations –Most are single user, SISO, downlink OFDM solutions –Training.
Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle.
Capstone Design Implementation of Depth Sensor Based on Structured Infrared Patterns June 11, 2013 School of Information and Communication Engineering,
Characterizing Processors for Energy and Performance Management Harshit Goyal and Vishwani D. Agrawal Department of Electrical and Computer Engineering,
LOW POWER DESIGN METHODS
Authors: Tong Lin, Kwen-Siong Chong, Joseph S. Chang, and Bah-Hwee Gwee Journal: IEEE Journal of Solid-State Circuits, vol. 48, no. 2, 2013 Presented by:
PERPETUAL IOT AWARENESS SYSTEM Intelligent Power Managing Middleware 25.
Hiba Tariq School of Engineering
Atoll Solutions PVT LTD
SmartCell: A Coarse-Grained Reconfigurable Architecture for High Performance and Low Power Embedded Computing Xinming Huang Depart. Of Electrical and Computer.
Texas Instruments TDA2x and Vision SDK
Ultra-Low-Voltage UWB Baseband Processor
Martin Croome VP Business Development GreenWaves Technologies.
Ultra-low Power for Always-on with Minima Dynamic Margining
Presentation transcript:

ULTRALEV: Ultra-Low-Energy Video Sensor Networks for IoT ($700B market) Technology Research Center University of Turku Finland

Image data DSP (compression) DSP (compression) CLOUD (analysis) CLOUD (analysis) Compressed Data Focal Plane Processor (Kovilta) μW DSP (U. Turku) CLOUD (analysis when necessary) CLOUD (analysis when necessary) Status Updates Data when necessary Target: 1 mW sensor node average power Compressed data

Open Questions Optics Energy-efficient radio (should support wide bit range) Focal-plane processor API & compiler SW libraries Applications

Technology / Consortium Kovilta (SME, FIN) – Focal-plane processors, vision algorithms Minima (SME, FIN) / U. Turku (FIN) – Microwatt, picojoule ultra-low voltage technology E.g. 7,5μW, 3 pJ/op, 2,4Mhz, 0,4V RISC Hurja (SME, FIN) – Vision algorithms, SW, API Institute of Information Theory and Automation (CZE) – Hardware, vision algorithms

BONUS SLIDES: TECHNOLOGY DETAILS

Kovilta – KOVA focal plane platform Massively parallel pixel- level processing on a Focal-Plane Processor ASIC: – Real-time sensor adaptation, filtering and segmentation. – Minimal delay and energy consumption overhead – Instant reaction to image content with radical reduction of output data on the sensor chip. – More videos at kovilta.fi

Turku Technology Research Center 0.4V, 5 Piko Joule / Operation RISC Cores – Adaptive architecture, – Zero-margin design – Wide voltage range (from 0.35V to 1V) Application-specific ultra-low power DSP – E.g. 20MHz, 100μW, 31 MFLOPS machine learning DSP Efficient on-chip power management circuits (DC-DC)

Comparison Against ARM State-of-the-Art ARM M0+ 1 U. Turku RISC Technology65nm28nm28nm FDSOI Native energy (pJ/op)11.7 (750kHz)3.1 (3MHz)5.6 (23MHz) Energy normalized to 28nm Regulated energy (pJ/op) Core energy over Temp. & VDDc DC-DC peak eff.80%-85% DC-DC eff. over Temp. & VDDc. 65%-75% System energy over Temp. & VDD (2*(0.8*23pj))/ nm 28nm 8 1) An 80nW retention 11.7pJ/cycle active subthreshold ARM Cortex-M0+ subsystem in 65nm CMOS for WSN applications (ISSCC 2015 paper 8.1)