Top Down Method The Deposition Process Author’s Note: Significant portions of this work have been reproduced and/or adapted with permission from material.

Slides:



Advertisements
Similar presentations
MICROELECTROMECHANICAL SYSTEMS ( MEMS )
Advertisements

Sputtering Eyal Ginsburg WW49/00.
Sputtering Eyal Ginsburg WW46/02.
Thermo-compression Bonding
FABRICATION PROCESSES
Chapter 2 Modern CMOS technology
For the exclusive use of adopters of the book Introduction to Microelectronic Fabrication, Second Edition by Richard C. Jaeger. ISBN © 2002.
ECE/ChE 4752: Microelectronics Processing Laboratory
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #6.
1 Microelectronics Processing Course - J. Salzman - Jan Microelectronics Processing Oxidation.
Vacuum Technology Need for Vacuum Environment
Ksjp, 7/01 MEMS Design & Fab IC/MEMS Fabrication - Outline Fabrication overview Materials Wafer fabrication The Cycle: Deposition Lithography Etching.
IC Fabrication and Micromachines
The Physical Structure (NMOS)
The Deposition Process

Physical Vapor Deposition
ECE/ChE 4752: Microelectronics Processing Laboratory
YoHan Kim  Thin Film  Layer of material ranging from fractions of nanometer to several micro meters in thickness  Thin Film Process 
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #5.
Thin Film Deposition Prof. Dr. Ir. Djoko Hartanto MSc
MEMs Fabrication Alek Mintz 22 April 2015 Abstract
Etching and Cleaning Cleaning remove contaminated layers Etching remove defect layers, form pattern by selective material removal Wet etching: using reactive.
Surface micromachining
1 ME 381R Fall 2003 Micro-Nano Scale Thermal-Fluid Science and Technology Lecture 18: Introduction to MEMS Dr. Li Shi Department of Mechanical Engineering.
Top Down Method Etch Processes
Plasma Etch and the MATEC Plasma Etcher Simulation
ES 176/276 – Section # 2 – 09/19/2011 Brief Overview from Section #1 MEMS = MicroElectroMechanical Systems Micron-scale devices which transduce an environmental.
McGill Nanotools Microfabrication Processes
CS/EE 6710 CMOS Processing. N-type Transistor + - i electrons Vds +Vgs S G D.
Thin Film Deposition Quality – composition, defect density, mechanical and electrical properties Uniformity – affect performance (mechanical , electrical)
반도체 제작 공정 재료공정실험실 동아대학교 신소재공학과 손 광 석 隨處作主立處開眞
INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #2. Chip Fabrication  Silicon Ingots  Wafers  Chip Fabrication Steps (FEOL, BEOL)  Processing Categories 
PVD AND CVD PROCESS Muhammed Labeeb.
1 Chemical Engineering Tools for Semiconductor Fabrication David Cohen, PhD AIChE Norcal Symposium April 12, 2005.
SEMINAR ON IC FABRICATION MD.ASLAM ADM NO:05-125,ETC/2008.
I.C. Technology Processing Course Trinity College Dublin.
Chapter Extra-2 Micro-fabrication process
SEMINAR PRESENTATION ON IC FABRICATION PROCESS
Top Down Method Photolithography Basics Author’s Note: Significant portions of this work have been reproduced and/or adapted with permission from material.
Reminders Quiz#2 and meet Alissa and Mine on Wednesday –Quiz covers Bonding, 0-D, 1-D, 2-D, Lab #2 –Multiple choice, short answer, long answer (graphical.
Top Down Manufacturing
Top Down Method Etch Processes
Introduction EE1411 Manufacturing Process. EE1412 What is a Semiconductor? Low resistivity => “conductor” High resistivity => “insulator” Intermediate.
Spencer/Ghausi, Introduction to Electronic Circuit Design, 1e, ©2003, Pearson Education, Inc. Chapter 3, slide 1 Introduction to Electronic Circuit Design.
Vacuum Technology.
Top Down Method Vacuum Applications in Nanomanufacturing Author’s Note: Significant portions of this work have been reproduced and/or adapted with permission.
CORPORATE INSTITUTE OF SCIENCE & TECHNOLOGY, BHOPAL DEPARTMENT OF ELECTRONICS & COMMUNICATIONS NMOS FABRICATION PROCESS - PROF. RAKESH K. JHA.
BY KRISHNAN.P Chemical Vapour Deposition (CVD) is a chemical process used to produce high purity, high performance solid materials. In a typical.
Lithography in the Top Down Method New Concepts Lithography In the Top-Down Process New Concepts Learning Objectives –To identify issues in current photolithography.
Etching: Wet and Dry Physical or Chemical.
LITHOGRAPHY IN THE TOP-DOWN PROCESS - BASICS
Vacuum Fundamentals Top Down Method Vacuum Technology Basics Author’s Note: Significant portions of this work have been reproduced and/or adapted with.
 Refers to techniques for fabrication of 3D structures on the micrometer scale  Most methods use silicon as substrate material  Some of process involved.
CMOS VLSI Fabrication.
CMOS FABRICATION.
Thin Film Deposition. Types of Thin Films Used in Semiconductor Processing Thermal Oxides Dielectric Layers Epitaxial Layers Polycrystalline Silicon Metal.
2-D Nanostructure Synthesis (Making THIN FILMS!)
Mar 24 th, 2016 Inorganic Material Chemistry. Gas phase physical deposition 1.Sputtering deposition 2.Evaporation 3.Plasma deposition.
Micro Electro Mechanical Systems (MEMS) Device Fabrication
ALD coating of porous materials and powders
Deposition Techniques
Top Down Method The Deposition Process
CMOS Fabrication CMOS transistors are fabricated on silicon wafer
Lecture 6 Metallization.
Lecture 4 Fundamentals of Multiscale Fabrication
PVD & CVD Process Mr. Sonaji V. Gayakwad Asst. professor
Deposition 27 and 29 March 2017 Evaporation Chemical Vapor Deposition (CVD) Plasma-Enhanced Chemical Vapor Deposition (PECVD) Metal Organometallic CVD.
Deposition Techniques 5 and 8 April 2019
Deposition 30 March And 1 April 2016
Presentation transcript:

Top Down Method The Deposition Process Author’s Note: Significant portions of this work have been reproduced and/or adapted with permission from material created by the Maricopa Advanced Technology Education Center, part of the Academic Affairs Division, Maricopa Community College District.

Learning Objectives The Student Will Be Able to Explain –The need for Deposition Processes in the Top Down Manufacturing Process –The methods used to perform physical and chemical deposition processes –The advantages of different deposition processes –The use of plasma for enhancing deposition

Purpose of Deposition Deposition places conductive or insulating layers on a substrate Deposition processes create locally conductive paths that can be used to interconnect devices Deposition can be used to build up more complex structures one layer at a time

Deposition Types Silicon Dioxide SiO 2 –Insulating layers –Protective coatings –Gate oxides Silicon Nitrides –Protective layers –Isolation

Deposition Types Polysilicon –Heavily doped silicon –Conductive –Used for interconnects and gate Metals –Aluminum/Aluminum-Copper –Tungsten –Titanium Alloys

Deposition Processes Physical or Chemical (or both?) –Physical Processes Deposit the material without chemical reactions –Chemical processes utilize liquid or vapor forms of precursors that react with the surface to form the desired deposition –It is possible to combine the processes and gain the benefits of each –Many processes are carried out in reduced pressure (partial vacuum) environments

Requirements of Deposition Since top-down processes may use many layers to form a product, any deposited layer must be compatible in many ways with what is below it –Film Stress –Conformality –Uniformity –Step Coverage –Thermal compatibility

Result of Non-Uniform Deposition From MATEC Module 61

Conformal Coverage Good Conformal Coverage Poor Conformal Coverage From MATEC Module 54

Step Coverage From MATEC Module 54

Physical Deposition Processes Sputtering –Plasma is created by RF or HV DC source –Inert gas such as Ar is used in a low pressure environment –Free electrons strike Ar atoms, causing positive ions to be formed –Negatively charged target material attracts ions –Ions dislodge particles that are deposited

Practice Questions 1. What are the two main types of deposition processes? Click once for each question. Physical and Chemical Deposition 2. What are commonly used metals for deposition? Aluminum, tungsten, and copper 3. What does conformality of a deposition refer to? The ability of the deposition to follow surface contours evenly

Sputtering Source:

Sputtering (3) Advantages –Low temperature process –Good Conformal Coating –Good Step Coverage Disadvantages –Dielectrics require RF Source –RF environment may affect other depositions

Evaporative Deposition Utilizes the principle of vapor pressure –Metallic species are melted in a low pressure environment –Higher vapor pressure metals evaporate first –Deposition of the vapor on the surface occurs –A low temperature process on the substrate –Alternatives include laser ablation Laser strikes a target, causing local melting

Evaporative Deposition (2) Advantages –Uniformly covers substrate –Simple process without chemicals or gases Disadvantages –Alloys are difficult to deposit Different metals have different vapor pressures –High aspect ratio features are difficult to cover Trajectory of evaporated particles tends to be vertical, which may not pattern sidewalls evenly

Practice Questions 1. Which physical deposition process uses plasma? Click once for each question. Sputtering 2. What is an advantage of sputtering? Low temperature process, good conformal coating 3. What is a disadvantage of evaporative deposition? Difficult to deposit alloys, difficult to get good high aspect ratio feature deposition

Spin On Coating A Physical Deposition Process –Similar to photoresist spin-on –Si-based liquid is applied –Coating is baked on to remove volatile liquid Used to planarize or flatten wafer surface –Can be patterned and etched for contacts Adds steps to process Alternatives – Chemical Mechanical Polish (if the objective is only to planarize surface)

Chemical Deposition Processes Wet or Dry? –Wet processes use liquids and immersion Electroplating Electroless deposition Wet growth of SiO2 insulating layer (water vapor) –Dry processes use chemical vapors Atmospheric Pressure Chemical Vapor Deposition Low Pressure Chemical Vapor Deposition Plasma Enhanced Chemical Vapor Deposition

Chemical Deposition Processes Atmospheric Chemical Vapor Deposition (CVD) –Wafers are heated –Chemical gases are introduced –A temperature dependent deposition rate –Mass transport limited at higher temperatures From MATEC Module 54

Chemical Deposition Processes Low Pressure (CVD) –Surface reaction limited at low pressure –Chamber may also be heated or unheated –Low pressure environment increases mean free path –Better Step Coverage and uniformity than APCVD From MATEC Module 54

Chemical Deposition Processes Plasma Enhanced Low Pressure (CVD) –Lower Temperature Process due to Plasma Enhancement –Dissociation of precursor gas molecules (Homogeneous reactions) –Ions bombard surface making it more reactive –Higher rates of deposition are possible than with LPCVD From MATEC Module 54

Chemical Deposition Processes Anti-reflective coatings –Reflection from shiny layers below photoresist causes blurred features –Utilize thin film deposition to create coatings that have λ/2 thickness at the exposure lamp wavelength –This results in destructive interference canceling reflection in the photoresist layer –Finer lithography is possible

Practice Questions 1. What are the advantages of atmospheric CVD? Click once for each question. Simple equipment requirements and batch processing is possible 2. What is an advantage of low pressure CVD? Improved purity of deposition and good step coverage 3. What is a principal advantage of plasma enhanced CVD? It is a lower temperature process than LPCVD

New Methods for Nanomanufacturing Thinner layers are necessary for higher speed transistors in IC design –Gate oxide thickness < 50 A –Approaches atomic layer dimensions Atomic Layer Deposition –A 2 step process of deposition and re-layering –SiOH* + SiCl4 →Si –O-SiCl3 + HCl –SiCl* + H2O → SiOH* + HCl

New Methods for Nanomanufacturing Molecular vapor deposition –Anti-stiction layers in MEMS are needed to avoid structures fusing to substrates –Vapor deposition of compounds avoids contamination found in liquid processes –Oxygen plasma clean operation precedes deposition process

LIGA Process LIGA includes X-Ray lithography, electroforming, and plating operations that construct high aspect ratio features on substrates –Precision patterning of a deposited PMMA resist layer using X-Ray lithography –Areas remaining after development are plated with metal –Photo resist and excess metal removed –Remaining features are high aspect ratio metal

Sources and References [1]Maricopa Advanced Techology Education Collaborative (2001) Module 54 “The Deposition Process” [2]Maricopa Advanced Technology Education Collaborative (2001) Module 61 “The Metallization Process” [3]Xaio, Hong (2001) Introduction to Semiconductor Manufacturing Technology, Prentice-Hall, Upper Saddle River, NJ, [4]S.M George, A.W. Ott, J.W. Klaus, J. Physics and Chemistry (1996) Vol 100, No. 31 [5] “ALD at TEAM WEIMER”, University of Colorado Boulder Chemical and Biological Engineering Department [6]Gordon, Hauseman, Kim, and Shepard (2003) Chem Vapor Deposition V9, No. 2 “A Kinetic Model for Step Coverage by Atomic Layer Deposition in Narrow Holes or Trenches” [7]Kobrin, Fuentes, Dasaradik Yi Nowak and Chinn (2004) SEMICON West, SEMI Technical Symposium [8]Mistry, Allen, Auth et al (2007) ‘A 45nM Logic Technology with High-k+ Metal Gate Transistors, Strained Silicon, 9 Cu Layers, 193nM Dry Patterning, and 100% Pb-free Packaging, Intel Corp, Hillsboro, OR, USA