MEMS 2016 Part 2 (Chapters 29 & 30) sami.franssila@aalto.fi

Surface MEMS

AFM tips: surface release Condition: Cr release etching must not attack Au or SU-8

Compressive stresses in film buckling Buckling depends on: 1) span on the structure: short beams do not buckle; 2) Stiffness of material: hard materials less prone than soft. 3) Stress level: thermal SiO2 is highly compressively stressed.

Tensile stress in film Tensile stress  flat membrane Desired stress state in most cases; however, too much tensile stress leads to cracking. Silicon nitride (1 GPa) ALD oxides (300 Mpa)

Released structural layers

Polysilicon Deposited by CVD at 625oC  true poly Can be deposited at 575oC  amorphous Anneal after deposition: a-Si  poly ! Typical thickness 1-2 µm Doping a) during deposition b) after deposition

Polysilicon doping Usually deposited undoped (practically insulator) Doping after deposition diffusion implantation Annealing ~950oC, 1 h to activate dopants Annealing changes film stress (and grain size) Heavy doping ca. 500 µΩ-cm (cf. Al 3 µ Ω-cm ) Grain size ca. 200-300 nm after anneal

Polysilicon stress anneal 580oC deposited film (a-Si) annealed differently, leading to different final stress

Marc Madou

Metal micromechanics (1)

Metal micromechanics (2)

Electroplated gold switch

Perforation to release large area structures

Stiction (sticking + friction) Capillary force of liquid exceeds mechanical strength of the released beam

Stiction prevention Replace water by something that has lower surface tension, like isopropyl alcohol Use stronger structures (H, T, I, U beams) Change structural material Redesign so that shorter beams needed Use more elaborate drying Use dry release  no drying needed

Alternative drying

Stiffening beam by 3D shaping

Stiction prevention: dry release Other dry releases: XeF2 dry etching of silicon SF6 isotropic plasma etching of silicon HF-vapor etching of oxide

Stiction prevention: dimples by three mask process

Cavity-SOI Most the 2nd wafer etched away Remaining Si of 2nd wafer oxide Al electrode Si membrane ground electrode air cavity Most the 2nd wafer etched away Remaining Si of 2nd wafer Bulk Si wafer

Cavity-SOI fabrication oxide Al electrode Si membrane ground electrode air cavity Silicon bulk wafer Lithography of air cavity DRIE of silicon & strip PR Cleaning Thermal oxidation Bonding with a 2nd wafer Thinning by KOH etching Al electrode sputtering Litho & Al etch & strip CVD oxide

No need for release etching. C-SOI: No need for release etching. Additional benefit of SOI: Single crystal silicon with superior mechanical properties, e.g. low stress

Bonded microphone Membrane chip with Au/Sn solder bumbs air gap Backplate chip with acoustic holes Membrane chip with Au/Sn solder bumbs acoustic holes air gap Franssila: Introduction to Microfabrication

IR spectrometer

CMOS-MEMS-bulk integration

CMOS-MEMS-SOI Dougherty, JMEMS 2003 a b c d Dougherty, JMEMS 2003 DRIE and semipermeable polysilicon deposition; buried oxide etching through semi-permeable poly deposition of standard polysilicon and CMP IC processing and release hole etching by DRIE

Types of MEMS Bulk MEMS: anisotropic wet or DRIE of bulk silicon SOI MEMS: DRIE or wet etching of SOI wafers Surface MEMS: thin films on top of a wafer Integrated MEMS: CMOS and MEMS on same chip

Bulk MEMS, wet etching

Bulk MEMS, DRIE a b c Deng, W. et al: Increase of electrospray throughput using multiplexed microfabricated sources for the scalable generation of monodisperse droplets, J. Aerosol Sci. 37 (2006) pp. 696–714

SOI MEMS

Surface MEMS  "Physics and Technology of Silicon Carbide Devices", book edited by Yasuto Hijikata, http://phys.org/news/2010-12-panasonic-imec-thin-packaged-mems.html

CMOS-MEMS: surface & bulk a) surface MEMS by front side dry plasma release; b) single crystal silicon MEMS by backside DRIE

CMOS-MEMS (2) If a fully processed CMOS wafer is used as a starting substrate for MEMS processing, what limitations are there ?

Summary Wafer selection: <100> SSP wafers ? <100> DSP wafers ? SOI wafers ? Materials compatibility: How high temperature does glass wafer tolerate ? Can cavity-SOI really be processed like standard wafer ? What are the limitations of piezoelectric materials ? Process-device interactions: Can thermal diffusion be used or is I/I preferred ? Is DRIE etch profile critical or non-critical Will the wafers bend due to thin film stresses ? Equipment and process capability: How can we clean wafers with released structures ? How thick roof can we deposit ? Can thick bonded wafer stacks be inserted to wafer boats ?

Summary (2) Design rules: What is the smallest allowed linewidth on front side ? What is the minimum linewidth for backside thru-wafer DRIE ? What is front-to-back alignment accuracy ? Mask considerations: Which photomasks are critical, which are non-critical ? Does etch undercutting need to be compensated on the mask ? Order of process steps: Should front side processing be completed before backside processing ? Can any steps be done after thin membrane formation ? Can any steps be done after thru-wafer holes have been made ? Reliability: How do stresses build up when more layers are deposited ? What vacuum does the resonator cavity need ? What leak rate is allowed in the resonator cavity ?