Presentation 3: Full Steam Ahead Advanced VLSI Design (ECE 1193) Kent Nixon, Tom Nason, Enes Eken, and Christopher Lukas January 31, 2013

Department of Electrical & Computer Engineering Project Goal Create a simulatable clone of the original Gameboy system using Mentor Graphics CAD tools.

Department of Electrical & Computer Engineering CPU (+ GPU + Audio) LCD VRAM Main RAM Cartridge (MC + ROM + RAM) Audio System Input Buttons Serial

Department of Electrical & Computer Engineering TOP STRUCTURE OF mcGAMEBOY

Department of Electrical & Computer Engineering Slave Master CPU (+ GPU + Audio Processors) Memory Controller CPU Logical Core LCD Controller (GPU) ROM On-Chip RAM Interrupt Controller Data Buffer Address Buffer Sprite RAM Audio Controller Clock Audio System Cartridge + Main RAM Input Buttons Serial I/O LCD Cartridge Serial Control

Department of Electrical & Computer Engineering Questions Answered VRAM and Main RAM –Where is the synchronization signal? There is none – data return times are deterministic (see later) Serial Communications –How to determine if we are master or slave? Accomplished via software CPU Logical Core –RISC or CISC? Variable instruction length (8- and 16-bit) -> CISC –Is there a cache of any form? Nope

Department of Electrical & Computer Engineering Work Accomplished Continued to read and learn about the Gameboy architecture Copied our design hierarchy into HDL Designer Set up a system where all team members have access to a single project file –Required modification of permissions on project directory –Also modified default file creation settings for group members so that all files created by a team member can be accessed by the rest of the team Created, compiled, and simulated our first sub-block (buttons)

Department of Electrical & Computer Engineering Buttons Accomplished Schematic of button in HDL Designer 8 buttons are read by 4 input bins

Department of Electrical & Computer Engineering Buttons ModelSim Graph

Department of Electrical & Computer Engineering Instruction Set Variable instruction length (1-3 bytes) 8-bit and 16-bit immediate values used Execution time (cycles) of instructions are known and deterministic No pipelining 4 cycles allowed for each byte of instruction

Department of Electrical & Computer Engineering x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF 0x 0x NOP LD BC,d LD (BC),A INC BC INC B 1 4 Z 0 H - DEC B 1 4 Z 1 H - LD B,d RLCA C LD (a16),SP ADD HL,BC H C LD A,(BC) DEC BC INC C 1 4 Z 0 H - DEC C 1 4 Z 1 H - LD C,d RRCA C 1x 1x STOP LD DE,d LD (DE),A INC DE INC D 1 4 Z 0 H - DEC D 1 4 Z 1 H - LD D,d RLA C JR r ADD HL,DE H C LD A,(DE) DEC DE INC E 1 4 Z 0 H - DEC E 1 4 Z 1 H - LD E,d RRA C 2x 2x JR NZ,r8 2 12/ LD HL,d LD (HL+),A INC HL INC H 1 4 Z 0 H - DEC H 1 4 Z 1 H - LD H,d DAA 1 4 Z - 0 C JR Z,r8 2 12/ ADD HL,HL H C LD A,(HL+) DEC HL INC L 1 4 Z 0 H - DEC L 1 4 Z 1 H - LD L,d CPL x 3x JR NC,r8 2 12/ LD SP,d LD (HL-),A INC SP INC (HL) 1 12 Z 0 H - DEC (HL) 1 12 Z 1 H - LD (HL),d SCF JR C,r8 2 12/ ADD HL,SP H C LD A,(HL-) DEC SP INC A 1 4 Z 0 H - DEC A 1 4 Z 1 H - LD A,d CCF C 4x 4x LD B,B LD B,C LD B,D LD B,E LD B,H LD B,L LD B,(HL) LD B,A LD C,B LD C,C LD C,D LD C,E LD C,H LD C,L LD C,(HL) LD C,A x 5x LD D,B LD D,C LD D,D LD D,E LD D,H LD D,L LD D,(HL) LD D,A LD E,B LD E,C LD E,D LD E,E LD E,H LD E,L LD E,(HL) LD E,A x 6x LD H,B LD H,C LD H,D LD H,E LD H,H LD H,L LD H,(HL) LD H,A LD L,B LD L,C LD L,D LD L,E LD L,H LD L,L LD L,(HL) LD L,A x 7x LD (HL),B LD (HL),C LD (HL),D LD (HL),E LD (HL),H LD (HL),L HALT LD (HL),A LD A,B LD A,C LD A,D LD A,E LD A,H LD A,L LD A,(HL) LD A,A x 8x ADD A,B 1 4 Z 0 H C ADD A,C 1 4 Z 0 H C ADD A,D 1 4 Z 0 H C ADD A,E 1 4 Z 0 H C ADD A,H 1 4 Z 0 H C ADD A,L 1 4 Z 0 H C ADD A,(HL) 1 8 Z 0 H C ADD A,A 1 4 Z 0 H C ADC A,B 1 4 Z 0 H C ADC A,C 1 4 Z 0 H C ADC A,D 1 4 Z 0 H C ADC A,E 1 4 Z 0 H C ADC A,H 1 4 Z 0 H C ADC A,L 1 4 Z 0 H C ADC A,(HL) 1 8 Z 0 H C ADC A,A 1 4 Z 0 H C 9x 9x SUB B 1 4 Z 1 H C SUB C 1 4 Z 1 H C SUB D 1 4 Z 1 H C SUB E 1 4 Z 1 H C SUB H 1 4 Z 1 H C SUB L 1 4 Z 1 H C SUB (HL) 1 8 Z 1 H C SUB A 1 4 Z 1 H C SBC A,B 1 4 Z 1 H C SBC A,C 1 4 Z 1 H C SBC A,D 1 4 Z 1 H C SBC A,E 1 4 Z 1 H C SBC A,H 1 4 Z 1 H C SBC A,L 1 4 Z 1 H C SBC A,(HL) 1 8 Z 1 H C SBC A,A 1 4 Z 1 H C Ax Ax AND B 1 4 Z AND C 1 4 Z AND D 1 4 Z AND E 1 4 Z AND H 1 4 Z AND L 1 4 Z AND (HL) 1 8 Z AND A 1 4 Z XOR B 1 4 Z XOR C 1 4 Z XOR D 1 4 Z XOR E 1 4 Z XOR H 1 4 Z XOR L 1 4 Z XOR (HL) 1 8 Z XOR A 1 4 Z Bx Bx OR B 1 4 Z OR C 1 4 Z OR D 1 4 Z OR E 1 4 Z OR H 1 4 Z OR L 1 4 Z OR (HL) 1 8 Z OR A 1 4 Z CP B 1 4 Z 1 H C CP C 1 4 Z 1 H C CP D 1 4 Z 1 H C CP E 1 4 Z 1 H C CP H 1 4 Z 1 H C CP L 1 4 Z 1 H C CP (HL) 1 8 Z 1 H C CP A 1 4 Z 1 H C Cx Cx RET NZ 1 20/ POP BC JP NZ,a / JP a CALL NZ,a / PUSH BC ADD A,d8 2 8 Z 0 H C RST 00H RET Z 1 20/ RET JP Z,a / PREFIX CB CALL Z,a / CALL a ADC A,d8 2 8 Z 0 H C RST 08H Dx Dx RET NC 1 20/ POP DE JP NC,a / CALL NC,a / PUSH DE SUB d8 2 8 Z 1 H C RST 10H RET C 1 20/ RETI JP C,a / CALL C,a / SBC A,d8 2 8 Z 1 H C RST 18H Ex Ex LDH (a8),A POP HL LD (C),A PUSH HL AND d8 2 8 Z RST 20H ADD SP,r H C JP (HL) LD (a16),A XOR d8 2 8 Z RST 28H Fx Fx LDH A,(a8) POP AF 1 12 Z N H C LD A,(C) DI PUSH AF OR d8 2 8 Z RST 30H LD HL,SP+r H C LD SP,HL LD A,(a16) EI CP d8 2 8 Z 1 H C RST 38H

Department of Electrical & Computer Engineering Instruction Set ALU Operations: ADD(C), SUB(C), AND, OR, XOR, CP (compare) [for immediates and registers] Load Operations: Register to Register, Memory to Register, Register to Memory (HL) Increments/Decrements Stack Operations (16-bit Push/Pop), Stack Pointer Addition Jumps, Calls, Returns, Resets (+conditionals) Rotates, Compliments BCD conversion (!)

Department of Electrical & Computer Engineering x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF 0x 0x RLC B 2 8 Z 0 0 C RLC C 2 8 Z 0 0 C RLC D 2 8 Z 0 0 C RLC E 2 8 Z 0 0 C RLC H 2 8 Z 0 0 C RLC L 2 8 Z 0 0 C RLC (HL) 2 16 Z 0 0 C RLC A 2 8 Z 0 0 C RRC B 2 8 Z 0 0 C RRC C 2 8 Z 0 0 C RRC D 2 8 Z 0 0 C RRC E 2 8 Z 0 0 C RRC H 2 8 Z 0 0 C RRC L 2 8 Z 0 0 C RRC (HL) 2 16 Z 0 0 C RRC A 2 8 Z 0 0 C 1x 1x RL B 2 8 Z 0 0 C RL C 2 8 Z 0 0 C RL D 2 8 Z 0 0 C RL E 2 8 Z 0 0 C RL H 2 8 Z 0 0 C RL L 2 8 Z 0 0 C RL (HL) 2 16 Z 0 0 C RL A 2 8 Z 0 0 C RR B 2 8 Z 0 0 C RR C 2 8 Z 0 0 C RR D 2 8 Z 0 0 C RR E 2 8 Z 0 0 C RR H 2 8 Z 0 0 C RR L 2 8 Z 0 0 C RR (HL) 2 16 Z 0 0 C RR A 2 8 Z 0 0 C 2x 2x SLA B 2 8 Z 0 0 C SLA C 2 8 Z 0 0 C SLA D 2 8 Z 0 0 C SLA E 2 8 Z 0 0 C SLA H 2 8 Z 0 0 C SLA L 2 8 Z 0 0 C SLA (HL) 2 16 Z 0 0 C SLA A 2 8 Z 0 0 C SRA B 2 8 Z SRA C 2 8 Z SRA D 2 8 Z SRA E 2 8 Z SRA H 2 8 Z SRA L 2 8 Z SRA (HL) 2 16 Z SRA A 2 8 Z x 3x SWAP B 2 8 Z SWAP C 2 8 Z SWAP D 2 8 Z SWAP E 2 8 Z SWAP H 2 8 Z SWAP L 2 8 Z SWAP (HL) 2 16 Z SWAP A 2 8 Z SRL B 2 8 Z 0 0 C SRL C 2 8 Z 0 0 C SRL D 2 8 Z 0 0 C SRL E 2 8 Z 0 0 C SRL H 2 8 Z 0 0 C SRL L 2 8 Z 0 0 C SRL (HL) 2 16 Z 0 0 C SRL A 2 8 Z 0 0 C 4x 4x BIT 0,B 2 8 Z BIT 0,C 2 8 Z BIT 0,D 2 8 Z BIT 0,E 2 8 Z BIT 0,H 2 8 Z BIT 0,L 2 8 Z BIT 0,(HL) 2 16 Z BIT 0,A 2 8 Z BIT 1,B 2 8 Z BIT 1,C 2 8 Z BIT 1,D 2 8 Z BIT 1,E 2 8 Z BIT 1,H 2 8 Z BIT 1,L 2 8 Z BIT 1,(HL) 2 16 Z BIT 1,A 2 8 Z x 5x BIT 2,B 2 8 Z BIT 2,C 2 8 Z BIT 2,D 2 8 Z BIT 2,E 2 8 Z BIT 2,H 2 8 Z BIT 2,L 2 8 Z BIT 2,(HL) 2 16 Z BIT 2,A 2 8 Z BIT 3,B 2 8 Z BIT 3,C 2 8 Z BIT 3,D 2 8 Z BIT 3,E 2 8 Z BIT 3,H 2 8 Z BIT 3,L 2 8 Z BIT 3,(HL) 2 16 Z BIT 3,A 2 8 Z x 6x BIT 4,B 2 8 Z BIT 4,C 2 8 Z BIT 4,D 2 8 Z BIT 4,E 2 8 Z BIT 4,H 2 8 Z BIT 4,L 2 8 Z BIT 4,(HL) 2 16 Z BIT 4,A 2 8 Z BIT 5,B 2 8 Z BIT 5,C 2 8 Z BIT 5,D 2 8 Z BIT 5,E 2 8 Z BIT 5,H 2 8 Z BIT 5,L 2 8 Z BIT 5,(HL) 2 16 Z BIT 5,A 2 8 Z x 7x BIT 6,B 2 8 Z BIT 6,C 2 8 Z BIT 6,D 2 8 Z BIT 6,E 2 8 Z BIT 6,H 2 8 Z BIT 6,L 2 8 Z BIT 6,(HL) 2 16 Z BIT 6,A 2 8 Z BIT 7,B 2 8 Z BIT 7,C 2 8 Z BIT 7,D 2 8 Z BIT 7,E 2 8 Z BIT 7,H 2 8 Z BIT 7,L 2 8 Z BIT 7,(HL) 2 16 Z BIT 7,A 2 8 Z x 8x RES 0,B RES 0,C RES 0,D RES 0,E RES 0,H RES 0,L RES 0,(HL) RES 0,A RES 1,B RES 1,C RES 1,D RES 1,E RES 1,H RES 1,L RES 1,(HL) RES 1,A x 9x RES 2,B RES 2,C RES 2,D RES 2,E RES 2,H RES 2,L RES 2,(HL) RES 2,A RES 3,B RES 3,C RES 3,D RES 3,E RES 3,H RES 3,L RES 3,(HL) RES 3,A Ax Ax RES 4,B RES 4,C RES 4,D RES 4,E RES 4,H RES 4,L RES 4,(HL) RES 4,A RES 5,B RES 5,C RES 5,D RES 5,E RES 5,H RES 5,L RES 5,(HL) RES 5,A Bx Bx RES 6,B RES 6,C RES 6,D RES 6,E RES 6,H RES 6,L RES 6,(HL) RES 6,A RES 7,B RES 7,C RES 7,D RES 7,E RES 7,H RES 7,L RES 7,(HL) RES 7,A Cx Cx SET 0,B SET 0,C SET 0,D SET 0,E SET 0,H SET 0,L SET 0,(HL) SET 0,A SET 1,B SET 1,C SET 1,D SET 1,E SET 1,H SET 1,L SET 1,(HL) SET 1,A Dx Dx SET 2,B SET 2,C SET 2,D SET 2,E SET 2,H SET 2,L SET 2,(HL) SET 2,A SET 3,B SET 3,C SET 3,D SET 3,E SET 3,H SET 3,L SET 3,(HL) SET 3,A Ex Ex SET 4,B SET 4,C SET 4,D SET 4,E SET 4,H SET 4,L SET 4,(HL) SET 4,A SET 5,B SET 5,C SET 5,D SET 5,E SET 5,H SET 5,L SET 5,(HL) SET 5,A Fx Fx SET 6,B SET 6,C SET 6,D SET 6,E SET 6,H SET 6,L SET 6,(HL) SET 6,A SET 7,B SET 7,C SET 7,D SET 7,E SET 7,H SET 7,L SET 7,(HL) SET 7,A

Department of Electrical & Computer Engineering Instruction Set 2nd set of operations display even more Opcode symmetry 3 bitwise operations: Test, Set, Reset Other register operations: Rotates, Shifts, Swap (upper/lower nibble)

Department of Electrical & Computer Engineering Audio Controller Audio Control Registers Audio Memory Quadrangular with Sweep and Envelope Quadrangular with Envelope Wave from RAM White Noise with Envelope Memory Controller Audio Synthesizer Audio System Cartridge

Department of Electrical & Computer Engineering

Responsibilities Team Member Technical Responsibilities Corporate Responsibilities Kent W. Nixon Serial, Memory Controller Color Selection Tom Nason CPU and Instruction Set Business Card Design Enes EkenCartridgePlay Testing Christopher LukasAudio Human Resource Management

Department of Electrical & Computer Engineering Plans for Next Week Test the tool flow from compiling to synthesizing to place and routing using our button module Split into the 2 groups of 2 as discussed –Tom and Chris can work together on getting the CPU up and running, and Enes and I can focus on the memory controller and routing out everything that goes along with that