TIMEPIX2 FE STUDIES X. Llopart

Summary of work done During summer I have been looking at a possible front end for Timepix2 The baseline schematic is based in the Medipix2 family FE but focusing in: –Low Noise (<70 e-) –Power (<10uW) –Area (< 1/4 th of pixel area: 27.5u x 27.5u) –Full chip minimum detectable charge (< 500e-) –Minimize TOT channel noise (ENC / (dV/dt) ) –Improved Peaking time (<25ns) –Bipolar input with leakage current compensation

From target specifications Timepix2 Pixel size55 µm x 55 µm Analog pixel area55 µm x [10…20] µm Pixel matrix256 x 256 Input chargeBipolar (h+ and e-) Leakage current compensationYES Peaking time≤ 25ns Return to zero (Tunable)< 5 Ke- TOT linearity and range< 500 Ke- Preamp output linear dynamic range< 40 Ke- Return to zero full chip spread (TOT spread)< 5% ENC (σ ENC )~75 e- Detector capacitance< 50 fF # Thresholds1 Discriminator response time< 2ns Full chip minimum detectable charge< 500 e- Threshold spread after tuning (see Figure 1)< 30 e- Pixel analog power consumption< V

“Classic schematic” Krummenacher amplifier with single ended preamp DC coupled discriminator (Vpreamp DC set at Vfbk) Discriminator VDDA=1.5 V

Preamp Summary Cd = 3fFCd = 10fF Peaking Time (Qin =1Ke-)21ns10ns ENC68 e-114 e- Gain46.4 µV/e-15.3 µV/e- Maximum Output Linear dynamic Range (~1V)~21 Ke-~65 Ke- Phase Margin75°69° DC Preamp output mismatch~6.5mV ( 140e-)~6.5mV ( 424e-) Qin=1 Ke-

Preamp (Cd=3fF)

Peaking Time Qin= 3Ke-

TOT and VoutPreamp Linearity Thr=~ 500e- Ikrum =2nA

TOT Noise (jitter) is defined as: –σ outnoise /slope The ENC (σ outnoise ) has to be minimized (Cf low) but the slope in system dependent (resolution vs ClockRef) TOT Noise (jitter)

TOT monotonic response One remaining issue is to ensure the TOT monotonic response for very large input charges (Qin > ~250 Ke-) Not enough input capacitance to store such large input charges Thinking on a hard reset of the FE but timming and digital coupling worries me… any idea?

Its is the Timepix discriminator: OTA + TRAFF (zero crossing) but with an input differential stage that gives: –Extra gain in first stage –Nice way to add the threshold equalizationDiscriminator

MC show a Threshold mismatch in the discriminator of ~5.5mV (~120e-)....Discriminator

Most of the specs for the preamp are achieved with the proposed design –TOT monotonicity is not respected (Qin > 250 Ke-) Discriminator also looks promising (sorry for the missing slides) No layout exist but looking through the transistor sizes it should be fissible inside the 1/4 th of the pixel areaConclusions