반도체 메모리 구조의 이해 Koo, Bon-Jae Dec. 5, 2007

Contents <Lecture 1> Chip Architecture DRAM Operation DRAM Process Integration <Lecture 2> Technology and Market Trends DRAM Cell Transistor Technology DRAM Cell Capacitor Technology

<Lecture 1> 1. Chip Architecture

Introduction SEC 80nm 2Gb DDR2 DRAM 2004 SEC 60nm 8Gb NAND Flash 2004 Ref[1] SEC 60nm 8Gb NAND Flash 2004 Ref[1] SEC 100nm 254Mb 1V DDR DRAM 2002 Ref[1]

Inside Memory Chip – Block / Cell Schematic Diagram of DRAM Chip WL BL Block (Cell Array) Core Circuit Block (Cell Array) Bank Chip (Die) Periphery Circuit Gate Storage Node Junction Ex) 512Mb = 4 Banks X 128Mb = 4 Banks X (26 X 30 Blocks) X 176kb = 4 Banks X (26 X 30 Blocks) X 352 WL X 500 BL&/BL Ref [3]

DRAM Chip Architecture Ref [1]

DRAM Chip Architecture Ref [1]

DRAM Chip Architecture – Vertical Structure (Ref [4]) (Ref [2]) STI / Active Gate / SAC DC / SNC (BC) / BL ILD1 / ILD2/ ILD3 Capacitor BEOL Metal Lines / IMD

DRAM Chip Architecture – Vertical Structure Ref [1]

2. DRAM Operation

DRAM Operation – Cell WL BL Block (Cell Array) Data Write Sequence (D1) BL (H) WL (H) – On WL (L) – Off BL (M) Data Read Sequence (D1) BL (M) WL (H) – On BL (M+a) ; a=DVBL WL (L) – Off

DRAM Operation –Charge Sharing Ref [3]

DRAM Operation – AC, Timing Data 1 Read (DR1) BL (Vcc/2) → Vcc/2+DVBL WL (Vpp) Vp (Vcc/2) VSN=Vcc Stand-by BL (Vcc/2) WL (0V) Vp (Vcc/2) VSN (arbitrary) Data 1 Write (DW1) BL (Vcc) WL (Vpp) Vp (Vcc/2) VSN→Vcc time V Vpp Vcc Vcc/2 Vss=0V BL WL SN Stand-by D1/D0 Write D1/D0 Read /RAS /CAS /WE + DATA WL Precharge BL Precharge /CS → DQ tRCD tRP tRDL BL

DRAM Operation – Bit-Line Sense Amplifier (BL SA) VCC Data 1 Read (DR1) H VCC WL (Vpp) BL (Vcc/2) → Vcc/2+DVBL ON ON VSN=Vcc Vp (Vcc/2) L 0V Ref [3] /BL GND VCC Data 0 Read (DR0) L 0V WL (Vpp) ON BL (Vcc/2) → Vcc/2-DVBL VSN=0 ON Vp (Vcc/2) H VCC /BL GND

DRAM Operation – Bit-Line Sense Amplifier (BL SA) Schematic Diagram of DRAM Chip S/A BL Core Circuit Cell Array Cell Array /BL Block (Cell Array) Bank Cell Array Cell Array Folded Bit-Line Chip (Die) Periphery Circuit S/A BL Cell Array Cell Array /BL BL /BL Cell Array Cell Array Open Bit-Line

DRAM Operation – Chip Operations (Ref [2]) Ref [4]

3. DRAM Process Integration

DRAM Processes - Integration STI Implantation Gate Oxidation Gate (Word Line) SAC DC BL (Bit Line) SNC CAP (SP/PP) BEOL (M1/VIA/M2) Ref [3]

DRAM Processes - STI STI (Shallow Trench Isolation) Pad Oxidation Mask Layer (SiN) CVD (ARC) PR Coating Photo (Exposure/Develop) Mask Layer D/E PR Strip Silicon Etch D/E Sidewall Oxidation (+Liner) STI Gap Fill CMP SiN Strip (H3PO4 WET) STI Silicon Active Wafer Gate Storage Node Junction cf) LOCOS

DRAM Processes – Well Formation Well Implantation Process Cell/Core NBAND IIP Peri PWELL IIP Cell/Core PWELL IIP Peri NWELL IIP Core NWELL IIP CMOS Circuit Transistor Characterizing PWELL Cell Core NMOS NWELL Core PMOS PWELL Peri NMOS NWELL Peri PMOS NBAND Bank Block (Cell Array) Schematic Diagram of DRAM Chip Core Circuit Periphery Circuit

DRAM Processes – Gate Oxide Pad Oxide Strip (WET) Gate Oxide (1) Growth PR Coating Photo (Exposure/Develop) Oxide Wet Strip PR Strip Gate Oxide (2) Growth Multiple Gate Oxide Thickness Thin/Medium/Thick Transistor Characterizing Thin GOX Thick GOX

DRAM Processes – Gate Gate Process Storage Node Junction Gate Process Gate Stack Deposition Poly Si / W(Wsix) / Mask SiN (ARC) PR Coating Photo Exposure / Develop Mask D/E PR Ashing/Strip W(Wsix) D/E Poly Si D/E Gate Spacer (SiN) Deposition Gate Spacer D/E Stopper (SiN) Deposition ILD (Interlayer Dielectric) Deposition CMP Gate Gate Spacer

DRAM Processes – SAC SAC (Self-Aligned Contact) Process (ARC) PR Coating Photo Exposure / Develop Oxide D/E (SAC Etch) PR Ashing/Strip SiN/Oxide D/E WET CLN Poly Si Deposition Poly Si CMP or Etch Back ILD (2) Deposition Direct Contact 이 불가능한 좁은 Contact Pitch 영역에 사용 (ex Cell) Mis-Align Immunity 가 좋음 SAC PAD

DRAM Processes – Direct Contact (DC) DC (Direct Contact) Process (ARC) PR Coating Photo Exposure / Develop Oxide D/E (SAC Etch) PR Ashing/Strip Contact Material (TiN/W) Deposition Etch Back (Node Separation) Cell DC Core/Peri DC

DRAM Processes – Bit-Line (BL) Bit-Line Process BL Material (TiN/W) Deposition Mask SiN Deposition (ARC) PR Coating Photo Exposure / Develop Mask (SiN) D/E PR Ashing/Strip TiN/W D/E BL Spacer (SiN) Depo BL Spacer D/E ILD (3) Depo / CMP BL

DRAM Processes – Storage Node Contact Storage Node Contact Process (ARC) PR Coating Photo Exposure / Develop Oxide D/E PR Ashing/Strip Poly Si Deposition / Etch Back Gate BL SNC DC SAC STI Wafer

DRAM Processes – Capacitor Capacitor Process (OCS) Stopper SiN Deposition Mold Oxide Deposition (ARC) PR Coating Photo Exposure/Develop Oxide D/E PR Ashing/Strip Stopper D/E Electrode (Poly or TiN..) Deposition Etch Back Oxide Strip Capacitor Dielectric Deposition (SiO2,AlO,HfO,ZrO…,HSG) Plate Poly Deposition Plate Poly Photo/Etch SP (Storage Node Poly) PP (Plate Poly) Cap. Dielectric Gate BL SNC DC SAC STI Wafer

DRAM Processes – Metal Lines / VIA (BEOL) Passivation SiN M2 VIA M1 MC IMD1 IMD2 BEOL ILD (4) Deposition / CMP PR Coating Metal Contact (MC) Photo MC Etch PR Ashing/Strip Metal (1) (Al) Deposition Metal (1) Photo/Etch IMD (Fox, low-k) Deposition VIA Photo/Etch Metal (2) Depo/Photo/Etch IMD Deposition Passivation SiN Deposition FAB OUT Ref [3]

Summary Chip Architecture DRAM Operation DRAM Process Integration Wafer Die (Chip) / Bank / Block / Cell 8F2 / 6F2 DRAM Vertical Structure DRAM Operation Data Read / Write Charge Sharing BL Sense Amplifier / SWD Timing Diagrams DRAM Process Integration FEOL : STI / WELL / Gate / SAC MEOL : DC / BL / SNC / Capacitor BEOL : Metal / VIA / Passivation

<Lecture 2> 4. Technology and Market Trends

Momentum of Memory Technology Innovation Ref [1]

Trend of DRAM Bit Density Ref [1]

Trend of Transistors Per Die Source: Intel Memory → High Density → Low Cost MPU → High Performance Ref [2]

Trend of Feature Sizes Feature Size Decreases → Chip Size Decreases (Low Cost) § Wafer Size Increases → High Density (512Mb/1Gb/4Gb…) Ref [2] Number of Transistors per Die Increases → Feature Size Decreases

Trend of Gate Length Scaling Ref [2] Gate Length ~ 70% of Feature Size Contacted Gate Pitch ~ 0.7x per 2 years ~ 2x transistor densities

DRAM Issues in Scaling Data Storage - Charges in Cell Capacitor - Data Loss ; Refresh Operation (64ms, 128ms) - Cell Transistor Junction Leakage - Capacitor Leakage Sensing Margin - Cell Capacitance - BL Parasitic Capacitance - Noise Speed - Cell Transistor Current - WL Loading Capacitance Process Issues - Lithography - Contact Not Open - Micro Bridge / Defects Reliability Issues

DRAM New Technologies Ref [4]

5. DRAM Cell Transistor Technology

Short Channel Effects Short Channel Effects Vgate Id On Off Lgate Log Id Vth Ioff Ref [3] Lgate Vth ~100nm Lgate Subthreshold Swing ~100nm

RCAT Process n p Recess Trench Etch (DR Size) Gate Patterning Active Pattern Shallow Trench Isolation Recess Trench Etch (DR Size) Gate Patterning p n Top View

FinFET DRAM Cell Cell Tr Vth for Ioff < 1fA Lgate Xj Gate Height (0.1um) Fin Width Lgate Gate Height Xj Channel Doping Concentrations (0.1um) Ref [10]

Structures of FinFET DRAM Damascene FinFET Local Damascene FinFET Passing Gate Ref [10]

Local Damascene FinFET Processes Plugged SiN Mask

Local Damascene FinFET Processes Plugged SiN Mask Acitive SiN Mask Ref [10]

Summary of DRAM Cell Transistor Technology Ref [4]

6. DRAM Cell Capacitor Technology

Capacitor General

Dielectric Materials and Thickness High-k Materials Ref [4]

DRAM Cell Capacitance Structures Ref [4]

DRAM Cell Capacitor Height and Mesh Structure Source: D-H Kim, IEDM 2004; K Kim, IEDM 2005 Mesh Capacitor Source: K Kim, IEDM 2005

Summary of DRAM New Technologies Technology and Market Trends Scaling Issues Cell Transistors Short Channel Effects Leakage Currents 3-Dimensional Cell Transistor Structures RCAT SRCAT SEG FinFET Cell Capacitors Capacitance Reduction High-k Dielectrics Mesh Capacitor Structure