CSE477 L06 Static CMOS Logic.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 06: Static CMOS Logic Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L06 Static CMOS Logic.2Irwin&Vijay, PSU, 2003 Review: CMOS Process at a Glance Define active areas Etch and fill trenches Implant well regions Deposit and pattern polysilicon layer Implant source and drain regions and substrate contacts Create contact and via windows Deposit and pattern metal layers  One full photolithography sequence per layer (mask)  Built (roughly) from the bottom up 4 metal 2 polysilicon 3 source and drain diffusions 1 tubs (aka wells, active areas) exception!

CSE477 L06 Static CMOS Logic.3Irwin&Vijay, PSU, 2003 CMOS Circuit Styles  Static complementary CMOS - except during switching, output connected to either V DD or GND via a low- resistance path l high noise margins -full rail to rail swing -V OH and V OL are at V DD and GND, respectively l low output impedance, high input impedance l no steady state path between V DD and GND (no static power consumption) l delay a function of load capacitance and transistor resistance l comparable rise and fall times (under the appropriate transistor sizing conditions)  Dynamic CMOS - relies on temporary storage of signal values on the capacitance of high-impedance circuit nodes l simpler, faster gates l increased sensitivity to noise

CSE477 L06 Static CMOS Logic.4Irwin&Vijay, PSU, 2003 Static Complementary CMOS V DD F(In 1,In 2,…In N ) In 1 In 2 In N In 1 In 2 In N PUN PDN PUN and PDN are dual logic networks … …  Pull-up network (PUN) and pull-down network (PDN) PMOS transistors only pull-up: make a connection from V DD to F when F(In 1,In 2,…In N ) = 1 NMOS transistors only pull-down: make a connection from F to GND when F(In 1,In 2,…In N ) = 0

CSE477 L06 Static CMOS Logic.5Irwin&Vijay, PSU, 2003 Threshold Drops V DD V DD  PDN 0  CLCL CLCL PUN V DD 0  CLCL V DD V DD  CLCL

CSE477 L06 Static CMOS Logic.6Irwin&Vijay, PSU, 2003 Threshold Drops V DD V DD  0 PDN 0  V DD CLCL CLCL PUN V DD 0  V DD - V Tn CLCL V DD V DD  |V Tp | CLCL S DS D V GS S SD D

CSE477 L06 Static CMOS Logic.7Irwin&Vijay, PSU, 2003 Construction of PDN  NMOS devices in series implement a NAND function  NMOS devices in parallel implement a NOR function A B A B AB A + B

CSE477 L06 Static CMOS Logic.8Irwin&Vijay, PSU, 2003 Dual PUN and PDN  PUN and PDN are dual networks l DeMorgan’s theorems A + B = A B [!(A + B) = !A !B or !(A | B) = !A & !B] A B = A + B [!(A B) = !A + !B or !(A & B) = !A | !B] l a parallel connection of transistors in the PUN corresponds to a series connection of the PDN  Complementary gate is naturally inverting (NAND, NOR, AOI, OAI)  Number of transistors for an N-input logic gate is 2N

CSE477 L06 Static CMOS Logic.9Irwin&Vijay, PSU, 2003 CMOS NAND A B A B AB ABF A B

CSE477 L06 Static CMOS Logic.10Irwin&Vijay, PSU, 2003 CMOS NOR A + B A B ABF AB A B

CSE477 L06 Static CMOS Logic.11Irwin&Vijay, PSU, 2003 Complex CMOS Gate OUT = !(D + A (B + C)) D A BC

CSE477 L06 Static CMOS Logic.12Irwin&Vijay, PSU, 2003 Complex CMOS Gate OUT = !(D + A (B + C)) D A BC D A B C

CSE477 L06 Static CMOS Logic.13Irwin&Vijay, PSU, 2003 Standard Cell Layout Methodology signals Routing channel V DD GND What logic function is this?

CSE477 L06 Static CMOS Logic.14Irwin&Vijay, PSU, 2003 OAI21 Logic Graph C AB X = !(C (A + B)) B A C i j j V DD X X i GND AB C PUN PDN A B C

CSE477 L06 Static CMOS Logic.15Irwin&Vijay, PSU, 2003 Two Stick Layouts of !(C (A + B)) ABC X V DD GND X CAB V DD GND uninterrupted diffusion strip crossover requiring vias

CSE477 L06 Static CMOS Logic.16Irwin&Vijay, PSU, 2003 Consistent Euler Path j V DD X X i GND AB C  For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)  An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph l Euler path: a path through all nodes in the graph such that each edge is visited once and only once.

CSE477 L06 Static CMOS Logic.17Irwin&Vijay, PSU, 2003 Consistent Euler Path j V DD X X i GND AB C ABC  An uninterrupted diffusion strip is possible only if there exists a Euler path in the logic graph l Euler path: a path through all nodes in the graph such that each edge is visited once and only once.  For a single poly strip for every input signal, the Euler paths in the PUN and PDN must be consistent (the same)

CSE477 L06 Static CMOS Logic.18Irwin&Vijay, PSU, 2003 OAI22 Logic Graph C AB X = !((A+B)(C+D)) B A D V DD X X GND AB C PUN PDN C D D A B C D

CSE477 L06 Static CMOS Logic.19Irwin&Vijay, PSU, 2003 OAI22 Layout BAD V DD GND C X  Some functions have no consistent Euler path like x = !(a + bc + de) (but x = !(bc + a + de) does!)

CSE477 L06 Static CMOS Logic.20Irwin&Vijay, PSU, 2003 XNOR/XOR Implementation A B A  B A B XNORXOR A  B A B A B  Can you create the stick transistor layout for the lower left circuit?  How many transistors in each?

CSE477 L06 Static CMOS Logic.21Irwin&Vijay, PSU, 2003 VTC is Data-Dependent A B F= A B AB M1M1 M2M2 M3M3 M4M4 Cint V GS1 = V B V GS2 = V A –V DS1 0.5  /0.25  NMOS 0.75  /0.25  PMOS  The threshold voltage of M 2 is higher than M 1 due to the body effect (  ) V Tn2 = V Tn0 +  (  (|2  F | + V int ) -  |2  F |) since V SB of M 2 is not zero (when V B = 0) due to the presence of Cint V Tn1 = V Tn0 D D S S weaker PUN

CSE477 L06 Static CMOS Logic.22Irwin&Vijay, PSU, 2003 Static CMOS Full Adder Circuit B BB BB B B B A A A A A A A A C in !C out !Sum

CSE477 L06 Static CMOS Logic.23Irwin&Vijay, PSU, 2003 Static CMOS Full Adder Circuit B BB BB B B B A A A A A A A A C in !C out !Sum !C out = !C in & (!A | !B) | (!A & !B) C out = C in & (A | B) | (A & B) !Sum = C out & (!A | !B | !C in ) | (!A & !B & !C in ) Sum = !C out & (A | B | C in ) | (A & B & C in )

CSE477 L06 Static CMOS Logic.24Irwin&Vijay, PSU, 2003 Next Time: Pass Transistor Circuits B A A  B

CSE477 L06 Static CMOS Logic.25Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l Pass transistor logic -Reading assignment – Rabaey, et al, presented by guest lecturer Greg Link  Reminders l I will be out of town Wed through Friday (so no office hours Wednesday this week, sorry) l HW#2 due September 30 th (next Tuesday) l Project specs (on-line) due October 9 th l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Only one midterm conflict filed for so far