GATE DIFFUSION INPUT: A low power digital circuit design By Khoirom Johnson Singh Under the guidance of Huirem Tarunkumar www.khoirom.wix.com/johnson DEPARTMENT OF ELECTRONICS AND COMMUNICATION, NIT MANIPUR

Content Introduction Literature Review Literature Review Conclusion Project Plan Project Progress Reference

1. Introduction What is power dissipation? The rate at which energy is taken from sources and converted into heat. Do we want heat in digital circuit/chips? No Then why?? Because it may cause circuit failure may be permanent or temporary. For every 10 degree Celsius rise in temperature roughly doubles the failure rate. So, it must be dissipated from the circuit to avoid increase in circuit temperature.

Why Low-power? High chip density (number of transistor increase) /Power density. High performance computing system characterized by large power dissipation. Increased market demand for portable consumer electronics powered by batteries. E.g. smartphones,tabs,laptops etc. Another major demand for low power chips comes from environmental concerns.

Early technology Complementary Metal Oxide Semiconductor Device(CMOS).

Complementary CMOS: A CMOS gate consists of two networks- the pull-up (PUN) and pull-down (PDN) network. n-inputs are distributed to both PUN & PDN. PUN: make a connection from VDD to F when F(a1,a2,….an)=1. PDN: make a connection from VDD to ground when F(a1,a2,…..an)=0. The PUN and PDN networks are constructed in a mutually exclusive fashion such that one and only one of the network is conducting in steady state. Fig1: CMOS logic gate

Rules for CMOS design A set of rules for CMOS implementation is: In case of AND function all PMOS are connected in parallel and NMOS are connected in series. In case of OR function all PMOS are connected in series and NMOS are connected in parallel. Fig 2: NMOS series(A.B) & parallel(A+B). Fig 3: PMOS parallel(A.B) & series(A+B).

Gate Diffusion Input(GDI) The GDI cell is almost similar to a CMOS inverter structure. In a CMOS inverter the source of PMOS is connected to VDD and the source of NMOS is grounded. A GDI cell consists of three inputs: G-common inputs to the gate of PMOS and NMOS N-input to the source/drain of NMOS P-input to the source/drain of PMOS One major difference between CMOS and GDI is that in GDI (N,P&G) terminals could be given a supply VDD or can be grounded or can be supplied with input signal depending upon the circuit to design and hence effectively minimizing the number of transistors used. Fig.4: GDI Cell Fig.5:CMOS inverter

Logic function (GDI) N P G OUT GATE 1 A 𝐴 NOT B AB AND A+B OR

2.Literature Review Title: Gate-Diffusion Input (GDI) : A Power- Efficient Method for Digital Combinatorial Circuits Authors: Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner IEEE Transactions on very large scale integration (VLSI) system, VOL.10,No.5 October 2002 Numerous logic gates and high-level digital circuits are implemented in various methods and process technologies and their simulation results are discussed. The power consumption is reduced by 45% as compared to CMOS. Lesser number of transistors are used in GDI technology. Lesser area as compared to CMOS.

Title: Gate Diffusion Input: A technique for fast digital circuits(implemented on 180nm technology) Author: Sudeshna Sarkar, Monika Jain, Arpita Saha, Amit Rathi IOSR Journal of VLSI and Signal Processing(IOSR-JVSP) Volume 4, Issue 2, Ver. IV(Mar-Apr. 2014), PP 49-53 e-ISSN: 2319 The GDI technique has been presented. Lesser number of gates to design a circuit which is desirable for fast and low power applications. Comparison between GDI and CMOS techniques has also depicted. The GDI technique can be successfully applied to larger digital circuits like adder.

Title: GDI Technique: A Power- Efficient Method for Digital Circuits. Authors: Kunal & Nidhi Kedia IJAEEE ISSN(print) : 2278-8948, Volume -1, Issue-3,2012 A novel GDI technique for low-power design was presented. The power consumption reduced by 45% as compared to CMOS technology. GDI will allow high density of fabrication.

Title: A Review on Gate Diffusion Input(GDI) Author: Jashanpreet Kaur, Navdeep Kaur and Amit Grover. International Journal of Advance Research in Electronics, Electrical & Computer Application of Engineering & Technology Vol.2, Issue 4, PP 385-391 July 2014 GDI is the advanced digital circuit designing technique in the market place today. It offers reduced area, less power consumption, high speed when compared to CMOS. GDI provides circuit design with reduced number of transistors.

3. Literature Review Conclusion GATES CMOS GDI INVERTER 2 OR 6 AND NOR 4 NAND XOR 12 XNOR 16 GDI provides less area of logic design as compared to CMOS logic design. The power consumption of GDI is reduced by 45% as compared to CMOS technology. Faster in speed up to 30% as compared to CMOS logic design. GDI provides circuit design with reduced number of transistors. Layout area is very small as compared to other logic design technologies. Bottom Line: Lesser number of transistors are the main factor for low power consumption. Fig 6: Transistor count comparison

4. Project Plan Performance and power dissipation Comparison Comparison of complex circuits in terms of power dissipation& delay using Cadence virtuoso. Implementation of complex circuit Implementation of complex digital circuits like Full-Adder in Cadence virtuoso. Power dissipation comparison (CMOS & GDI) NOT, OR, AND, NAND, NOR&XOR logic gates in Cadence virtuoso. Implementation of various logic gates(CMOS & GDI) NOT, OR, AND, XOR, NAND & NOR logic gates in Cadence virtuoso.

5. Project Progress CMOS INVERTER, AND & OR Logic designs are implemented Fig 7: SCHEMATIC DIAGRAM FOR CMOS INVERTER.

TRANSIENT ANALYSIS FOR CMOS INVERTER AND DYNAMIC POWER DISSIPATION OUT 1 Fig 8: Transient analysis of CMOS inverter.

SCHEMATIC DIAGRAM FOR CMOS AND LOGIC DESIGN Fig 9: Schematic diagram for CMOS AND logic design

TRANSIENT ANALYSIS FOR CMOS AND Logic design & its DYNAMIC POWER DISSIPATION IN OUT 1 Fig 10: Transient analysis of CMOS AND logic design.

SCHEMATIC DIAGRAM FOR CMOS OR LOGIC DESIGN Fig 11: Schematic diagram for CMOS OR logic design.

TRANSIENT ANALYSIS FOR CMOS OR Logic design & its DYNAMIC POWER DISSIPATION IN OUT 1 Fig 12: Transient analysis of CMOS OR logic design

Paper Acceptance Title: “A Review on Gate Diffusion Input (GDI): A New Method for Rapid Digital Circuits” International Conference on “EMERGING TRENDS IN SCIENCE AND ENGINEERING RESEARCH (ETSER-2015)” 2-4 December 2015 NATIONAL INSTITUTE OF TECHNOLOGY MANIPUR Copyright © 2015 by khoirom Johnson singh

6. References [1] A. Morgenshtein, A. Fish and I.A. Wagner, “Gate diffusion input (GDI) a power- efficient method for Digital Combinatorial Circuit,” Journal of IEEE Trans. On VLSI System, Vol.10, pp. 566-581, Oct. 2002. [2] Kunal and Nidhi Kedia “ GDI Technique: A power-efficient method for digital circuits” Journal of IJAEEE Vol-1, Issue-3, 2012, ISSN (print): 2278-8948. [3] Sudeshna Sarkar, Monika Jain, Arpita Saha and Amit Rathi “ Gate diffusion input: A new technique for fast digital circuit” Journal of IOSR-JVSP, Vol 2, Issue 2, Ver. IV (Mar-Apr, 2014), pp 49-53. [4] Jashanpreet Kaur, Navdeep Kaur and Amit Grover “ A Review on Gate Diffusion input (GDI)”Vol, 2 issue 4, July 2014, PP 385-391. [5] Digital Integrated Circuits by Jan M. Rabaey, Anantha Chandrakasan and Borivoje Nikolic, 2nd edition, ISBN-978-81-203-2257-8. [6] R. Uma and P. Dhavachelvan “ Modified Gate Diffusion input technique: A new technique for enhancing performance in full adder circuits”. 2nd International conference on communication, computing and security [ICCCS-2012].

Thank You For Your Time End of Slide (KHURUMJARI) Copyright © 2015 by khoirom Johnson singh