Data Flow and Behavioral Modeling in VHDL 1 MS EMBEDDED SYSTEMS

Data Flow Modeling A data flow style architecture models the hardware in terms of the movement of data over continuous time between combinational logic components such as adders, decoders and primitive logic gates. It describes the Register Transfer Level behavior of a circuit. It utilizes Logical and Relational Operators and Concurrent assignment statements. This style is not appropriate for modeling of sequential logic. It is best applied in the modeling of data driven circuit elements such as an Arithmetic Logic Unit. MS EMBEDDED SYSTEMS

Concurrent Assignment Statement These Statements share the property that the order in which they appear in VHDL code does not affect the meaning of the code Sequential Assignment Statement: The ordering of the statements may affect the meaning of the code 3 MS EMBEDDED SYSTEMS

Half adder library ieee; use ieee.std_logic_1164.all; entity halfadder is port(a,b: in std_logic; s,cout: out std_logic); end halfadder; architecture ha of halfadder is begin s <= a xor b; cout <=a and b; end ha; MS EMBEDDED SYSTEMS

Half subtractor library ieee; use ieee.std_logic_1164.all; entity halfsub is port(a,b: in std_logic; diff,borr: out std_logic); end halfsub; architecture hsub of halfsub is begin diff<= a xor b; borr <= (not )a and b; end ha; MS EMBEDDED SYSTEMS

Full Adder library ieee; use ieee.std_logic_1164.all; entity fulladder is port(a,b, cin : in std_logic; s,cout: out std_logic); end fulladder; architecture fa of fulladder is begin s <= a xor b xor cin; cout <=(a and b)or ( b and cin) or (cin and a); end fa; MS EMBEDDED SYSTEMS

Rules For Logical Operators MS EMBEDDED SYSTEMS

Logic Operators Logic operators andornandnorxornotxnor Logic operators precedence Highest not andornandnorxorxnor Lowest MS EMBEDDED SYSTEMS

No Implied Precedence Wanted: Y = ab + cd Incorrect Y <= a and b or c and d equivalent to Y <= ((a and b) or c) and d equivalent to Y = (ab + c)d Correct Y <= (a and b) or (c and d) MS EMBEDDED SYSTEMS

Concatenation signal A: STD_LOGIC_VECTOR(3 downto 0); signal B: STD_LOGIC_VECTOR(3 downto 0); signal C, D, E: STD_LOGIC_VECTOR(7 downto 0); A <= ”0000”; B <= ”1111”; C <= A & B;-- C = ” ” D <= ‘0’ & ” ”;-- D <= ” ” E <= ‘0’ & ‘0’ & ‘0’ & ‘0’ & ‘1’ & ‘1’ & ‘1’ & ‘1’; -- E <= ” ” MS EMBEDDED SYSTEMS

Concurrent Signal Assignment Statements Functional Modeling Implements Simple Combinational Logic Concurrent Signal Assignment Statements Are an Abbreviated Form of Processes - Conditional signal assignment statements - Selected Signal Assignment Statements MS EMBEDDED SYSTEMS

Conditional Signal assignment Allows a signal to be set to one of several values WHEN-ELSE statement LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux2to1 IS PORT ( w0, w1, s: IN f: OUT END mux2to1 ; to-1 multiplexer STD_LOGIC ; STD_LOGIC ) ; “w0” will assigned to “f” ARCHITECTURE Behavior OF mux2to1 IS when “s” is ‘0’, otherwise, BEGIN “w1” assigned to “f” f <= w0 WHEN s = '0' ELSE w1 ; END Behavior ; MS EMBEDDED SYSTEMS

Comparator entity compare is (port a, b: in std_logic_vector(3 downto 0); aeqb, agtb, altb : out std_logic ); end compare; architecture compare1 of compare is begin aeqb b else ‘0’’; altb<= ‘1’ when a <b else ‘0’; end compare1; MS EMBEDDED SYSTEMS

Conditional Signal Assignment Examples a <= b; a <= ‘0’ AFTER 10 ns ; x <= a AND b OR c ; y <= a AFTER 1 ns WHEN x = y ELSE b ; z <= a AND b, c AFTER 5 ns, ‘1’ AFTER 30 ns WHEN NOW < 1 ms ELSE ‘0’, a AFTER 4 ns, c OR d AFTER 10 ns; MS EMBEDDED SYSTEMS

2 Input NAND Gate ENTITY nand2 IS PORT (a, b: IN BIT; z: OUT BIT); END nand2; ARCHITECTURE no_delay OF nand2 IS BEGIN z <= a NAND b; END no_delay; MS EMBEDDED SYSTEMS

2:1 MUX ENTITY Mux2x1 IS PORT (a0, a1, sel: IN BIT; z: OUT BIT); END Mux2x1; ARCHITECTURE conditional OF Mux2x1 IS BEGIN z <= a0 WHEN sel = ‘0’ ELSE a1; END conditional; MS EMBEDDED SYSTEMS

Selected signal assignment Allows a signal to be assigned one of several values, based on a selection criterion Examples: can be used to implement multiplexer WITH-SELECT statement MS EMBEDDED SYSTEMS

Selected Signal Assignment WITH expression SELECT target <= selected_waveforms ; selected_waveforms ::= { waveform WHEN choices, } waveform WHEN choices choices ::= choice { | choice } choice ::= expression | range | simple_name | OTHERS MS EMBEDDED SYSTEMS

VHDL Models For A Multiplexer I0 I1 I2 I3 MUF X A B F <= (not A and not B and I0) or (not A and B and I1) or (A and not B and I2) or (A and B and I3); MUX model using a conditional signal assignment statement : F <= I0 when Sel = 0 else I1 when Sel = 1 else I2 when Sel = 2 else I3; MS EMBEDDED SYSTEMS

4-to-1 Multiplexer LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY mux4to1 IS PORT ( w0, w1, w2, w3: IN s: IN f: OUT END mux4to1 ; ARCHITECTURE Behavior OF mux4to1 IS BEGIN WITH s SELECT f <= w0 WHEN "00", w1 WHEN "01", w2 WHEN "10", w3 WHEN OTHERS ; END Behavior ; STD_LOGIC ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ) ; Selection based on value of signal “s”. For example, when “s” is “00”, value of “w0” will assigned to “f” MS EMBEDDED SYSTEMS

2-to-4 binary decoder LIBRARY ieee ; USE ieee.std_logic_1164.all ; ENTITY dec2to4 IS PORT ( w: IN En: IN y: OUT END dec2to4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(0 TO 3) ) ; Concatenation: ARCHITECTURE Behavior OF dec2to4 IS SIGNAL Enw : STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Enw <= En & w ; WITH Enw SELECT y <= "1000" WHEN "100", "0100" WHEN "101", "0010" WHEN "110", "0001" WHEN "111", "0000" WHEN OTHERS ; END Behavior ; Enw(2) <= En; Enw(1) <= w(1); Enw(0) <= w(0); “y” will be assigned with different values based on value of “Enw” MS EMBEDDED SYSTEMS

ALU Design entity ALU is Port ( a,b: in std_logic_vector( 7 downto 0); sel: in std_logic_vector( 3 downto 0); cin : in std_logic; y:out std_logic_vector( 7 downto 0)); end ALU; architecture dataflow of ALU is Signal arith, logic: std_logic_vector( 7 downto 0); begin MS EMBEDDED SYSTEMS

ALU Design // Arithmetic Unit with sel( 2 downto 0) select arith <= a when “000”, a+1 when “001”, a-1 when “010”, b when “011”, b+1 when “100”, b-1 when “101”, a+b when “110”, a+b+cin when others; MS EMBEDDED SYSTEMS

ALU Design // Logical unit With sel( 2 downto 0) select logic<= not a when “000”, not b when “001”, a and b when “010”, a or b when “011”, a nand b when “100”, a nor b when “101”, a xor b when “110”, a when others; MS EMBEDDED SYSTEMS

ALU Design // Multiplexer With sel (3) select Y<= arith when ‘0’, logic when others; end dataflow; MS EMBEDDED SYSTEMS

8 bit adder entity adder_8bit is Port( a, b: in std_logic_vector( 7 downto 0); sum: out std_logic_vector( 7 downto 0); end adder_8bit; architecture archi of adder_8bit is begin Sum <= a + b; end archi; MS EMBEDDED SYSTEMS

Behavioral Modeling The Behavioral style architecture contains concurrent statements with sections of sequential statements that describes the output of the circuit at a discrete moment in time given particular inputs. The aspects of VHDL that are most relevant to the behavioral style architectures include the following: (1) Process statements and sensitivity lists. (2) Sequential statements (3) Variables. The behavior style is used to describe both sequential and combinational circuits.Hence it is a valuable design approach for FSM’s or any control logic. MS EMBEDDED SYSTEMS

PROCESS Statement This statement is used to separate sequential statement in VHDL from concurrent statement. It encloses a section of sequential statements that exists inside an architecture. Can have more than one process in an architecture, the processes interact concurrently Only Exist Within a Process and Are Executed Sequentially A Process, Even Though It Is Composed of Multiple Sequential Statements, Is a Single Concurrent Statement for Simulation Purposes MS EMBEDDED SYSTEMS

Process Statement [process_label:] PROCESS [(signal_name {, signal_name})]-- Sensitivity list [VARIABLE declarations] BEGIN [WAIT statement] [Simple signal assignment statements] [Variable assignment statements] [IF statements] [CASE statements] [LOOP statements] END PROCESS [process_label]; 29 MS EMBEDDED SYSTEMS

Using Sequential code to design combinational circuits Rule 1:Make sure that all input signals used(read) in the process appear in its sensitivity list Rule2:Make sure that all combinations of input/output signals are included in the code that is make sure that by looking at the code the complete truth table can be obtained 30 MS EMBEDDED SYSTEMS

Case Statement : example 1 entity multiplexer is port ( muxselect : in integer ; in_0, in_1, in_2, in_3 : in bit ; muxout : out bit ) ; end multiplexer ; architecture mux41 of multiplexer is begin p1:process(muxselect,in_0, in_1, in_2, in_3 ) begin case muxselect is when 0 => muxout muxout muxout <= in_2 ; when 3 => muxout muxout<=‘0’; end case ; end process p1; end mux41; MS EMBEDDED SYSTEMS

Alternative style entity mux21 is Port(w0,w1,s:in std_logic; f:out std_logic); end mux21; architecture beh of mux21 is begin Process(w0,w1,s) begin f<=w0; If s=‘1’ then f<=w1;end if; end process; end beh; 32 MS EMBEDDED SYSTEMS

Example 2 :2-to-4 binary decoder Process will be executedLIBRARY ieee ; when valueUSE ieee.std_logic_1164.all ; of “w” orENTITY dec2to4 IS “En” changePORT (w: IN En: IN y: OUT END dec2to4 ; STD_LOGIC_VECTOR(1 DOWNTO 0) ; STD_LOGIC ; STD_LOGIC_VECTOR(0 TO 3) ) ; “y” assigned with ARCHITECTURE Behavior OF dec2to4 IS BEGIN PROCESS ( w, En ) BEGIN IF En = '1' THEN CASE w IS WHEN "00" => WHEN "01" => WHEN "10" => WHEN OTHERS => END CASE ; ELSE y <= "0000" ; END IF ; END PROCESS ; END Behavior ; different value based on value of “w” y <= "1000" ; y <= "0100" ; y <= "0010" ; y <= "0001" ; MS EMBEDDED SYSTEMS

Sensitivity Clause process ( clk, clr )process begin wait on clk, clr ; end ; MS EMBEDDED SYSTEMS

Examples on wait statements entity dff is port( d, clk: in std_logic; q : out std_logic); end dff; architecture behave of dff is begin process begin wait until clk'event and clk = '1'; q <= d; end process; end behave; MS EMBEDDED SYSTEMS

Rising Edge D Flipflop entity dff is port ( data, clk: in std_logic; q:out std_logic); end dff; architecture behav of dff is begin process(clk) begin If( clk' event and clk= ‘1’) then q<= data; end if; end process; end behav; MS EMBEDDED SYSTEMS

Rising edge DFF With Asynchronous reset entity dff_asyncrst is port ( data, clk, rst: in std_logic; q:out std_logic); end dff_asyncrst; architecture behav of dff_asyncrst is begin process( clk, rst) begin if( rst=‘0’) then q<=‘0’; elsif( clk 'event and clk=‘1’ ) then q<= data; end if; end process; end behav; MS EMBEDDED SYSTEMS

Rising edge DFF With Asynchronous Preset MS EMBEDDED SYSTEMS

Rising edge DFF With Asynchronous Preset entity dff_asyncprst is port ( data, clk, prst: in std_logic; q:out std_logic); end dff_asyncprst; architecture behav of dff_asyncprst is begin process( clk, prst) begin if( prst=‘0’) then q<=‘1’; elsif( clk 'event and clk=‘1’ ) then q<= data; end if; end process; end behav; MS EMBEDDED SYSTEMS

Rising edge FF with Asynchronous reset and preset MS EMBEDDED SYSTEMS

Rising edge FF with Asynchronous reset and preset entity dff_pre is port ( data, clk, reset, preset : in std_logic; q:out std_logic); end dff_pre; architecture behav of dff_pre is begin process( clk, reset, preset) begin If(reset=‘0’) then Q<=‘0’; elsif( preset =‘1’) then Q<=‘1’; elsif ( clk' event and clk= ‘1’) then Q<=data; end if; end process; End behav; MS EMBEDDED SYSTEMS

DFF with synchronous reset MS EMBEDDED SYSTEMS

DFF with synchronous reset entity dff_syncrst port( data,clk,reset: in std_logic; q:out std_logic); end dff_syncrst; architecture behav1 of dff_syncrst is begin process (clk) begin if (clk' event and clk =‘1’) then q<=‘0’; else q<=data; end if; end process; end behav1; MS EMBEDDED SYSTEMS

D Latch with data and enable MS EMBEDDED SYSTEMS

D Latch with data and enable entity d_latch is port( enable, data: in std_logic; y:out std_logic); end d_latch; architecture behav of d_latch is begin Process(enable, data) begin if(enable = ‘1’) then y<=data; end if; end process; end behav; MS EMBEDDED SYSTEMS

4 bit up counter with Asynchronous clear entity counter is port( clk, clr: in std_logic; q: out std_logic_vector( 3 downto 0)); end counter; architecture archi of counter is signal tmp: std_logic_vector( 3 downto 0); begin process( clk, clr) if( clr=‘1’) then tmp<= “0000”; MS EMBEDDED SYSTEMS

4 bit up counter with Asynchronous clear elsif( clk’event and clk=‘1’) then tmp<= tmp+1; end if; end process; Q<= tmp; end archi; MS EMBEDDED SYSTEMS

4 bit down counter with synchronous set entity counter2 is Port( clk, set: in std_logic; q: out std_logic_vector( 3 downto 0)); end counter2; architecture archi of counter2 is Signal tmp: std-logic-vector( 3 downto 0); begin process(clk) begin if( clk’event and clk=‘1’) then MS EMBEDDED SYSTEMS

4 bit down counter with synchronous set If( s=‘1’) then tmp <= “1111”; else tmp<= tmp-1; end if; end if; end process; Q<=tmp; end archi; MS EMBEDDED SYSTEMS

4 bit up down counter with Asynchronous clear entity counter3 is port( clk, clr, updown: in std_logic; q: out std_logic-vector( 3 downto 000; end counter3; architecture archi of counter3 is Signal tmp: std_logic_vector( 3 downto 0); begin Process( clk, clr) Begin if ( clr=‘1’) then MS EMBEDDED SYSTEMS

4 bit up down counter with Asynchronous clear tmp<=“0000”; elsif( clk’event and clk=‘1’) then if (updown=‘1’) then tmp<= tmp+1; else tmp<= tmp-1; end if; end if; end process; q<=tmp; end archi; MS EMBEDDED SYSTEMS

Adder/Subtractor 52 MS EMBEDDED SYSTEMS

Adder/Subtractor LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_arith.ALL; USE ieee.std_logic_unsigned.ALL; ENTITY AddSub IS GENERIC(n: NATURAL :=8); -- default number of bits = 8 PORT(A: IN std_logic_vector(n-1 downto 0); B: IN std_logic_vector(n-1 downto 0); subtract: IN std_logic; carry: OUT std_logic; sum: OUT std_logic_vector(n-1 downto 0)); END AddSub; 53 MS EMBEDDED SYSTEMS

Adder/Subtractor ARCHITECTURE Behavioral OF AddSub IS -- temporary result with one extra bit for carry SIGNAL result: std_logic_vector(n downto 0); BEGIN PROCESS(subtract, A, B) BEGIN IF (subtract = '0') THEN -- addition --add the two operands with one extra bit for carry result <= ('0' & A)+('0' & B); sum <= result(n-1 downto 0); -- extract the n-bit result carry <= result(n); -- extract the carry bit from result ELSE -- subtraction result <= ('0' & A)-('0' & B); sum <= result(n-1 downto 0); -- extract the n-bit result carry <= result(n); -- extract the borrow bit from result END IF; END Behavioral; 54 MS EMBEDDED SYSTEMS

ALU Design LIBRARY ieee; USE ieee.std_logic_1164.all; -- The following package is needed so that the STD_LOGIC_VECTOR signals -- A and B can be used in unsigned arithmetic operations. USE ieee.std_logic_unsigned.all; ENTITY alu IS PORT ( S: IN std_logic_vector(2 downto 0); -- select for operations A, B: IN std_logic_vector(3 downto 0); -- input operands F: OUT std_logic_vector(3 downto 0)); -- output END alu; ARCHITECTURE Behavior OF alu IS BEGIN PROCESS(S, A, B) 55 MS EMBEDDED SYSTEMS

ALU Design BEGIN CASE S IS WHEN "000" => -- pass A through F <= A; WHEN "001" => -- AND F <= A AND B; WHEN "010" => -- OR F <= A OR B; WHEN "011" => -- NOT A F <= NOT A; WHEN "100" => -- add F <= A + B; WHEN "101" => -- subtract F <= A - B; 56 MS EMBEDDED SYSTEMS

ALU Design WHEN "110" => -- increment F <= A + 1; WHEN OTHERS => -- decrement F <= A - 1; END CASE; END PROCESS; END Behavior; 57 MS EMBEDDED SYSTEMS

3-to-8 decoder LIBRARY ieee; USE IEEE.std_logic_1164.all; ENTITY Decoder IS PORT( E: IN std_logic; -- enable A: IN std_logic_vector(2 DOWNTO 0); -- 3 bit address Y: OUT std_logic_vector(7 DOWNTO 0)); -- data bus output END Decoder; ARCHITECTURE Behavioral OF Decoder IS BEGIN PROCESS (E, A) 58 MS EMBEDDED SYSTEMS

3-to-8 decoder BEGIN IF (E = '0') THEN -- disabled Y '0'); -- 8-bit vector of 0 ELSE CASE A IS -- enabled WHEN "000" => Y Y Y Y Y Y Y Y <= " “; 59 MS EMBEDDED SYSTEMS

3-to-8 decoder WHEN OTHERS => NULL; END CASE; END IF; END PROCESS; END Behavioral; 60 MS EMBEDDED SYSTEMS

Priority Encoder Entity priority is Port (w:in std_logic_vector(3 downto 0); y:out std_logic_vector(1 downto 0); z:out std_logic); End priority; architecture beh of priority is Begin y<= “11” when w(3) =‘1’ else “10” when w(2)=‘1’ else “01” when w(1)= ‘1’ else “00”; Z<=‘0’ when w=“0000” else ‘1’; End behavior; 61 MS EMBEDDED SYSTEMS

8 bit wide Tristate buffer LIBRARY ieee; USE IEEE.std_logic_1164.ALL; ENTITY TriState_Buffer IS PORT ( E: IN std_logic; d: IN std_logic_vector(7 DOWNTO 0); y: OUT std_logic_vector(7 DOWNTO 0)); END TriState_Buffer; ARCHITECTURE Behavioral OF TriState_Buffer IS BEGIN PROCESS (E, d) BEGIN IF (E = '1') THEN y <= d; ELSE y 'Z'); -- to get 8 Z values END IF; END PROCESS; END Behavioral; 62 MS EMBEDDED SYSTEMS

BCD to Seven segment decoder LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY bcd IS PORT ( I: IN STD_LOGIC_VECTOR (3 DOWNTO 0); Segs: OUT std_logic_vector (1 TO 7)); END bcd; ARCHITECTURE Behavioral OF bcd IS BEGIN PROCESS(I) BEGIN 63 MS EMBEDDED SYSTEMS

BCD to Seven segment decoder CASE I IS WHEN "0000" => Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs Segs <= " "; END CASE; END PROCESS; END Behavioral; 64 MS EMBEDDED SYSTEMS

Signed Multiplier library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity signed_mult is port ( a b result ); end entity; : in signed (7 downto 0); : in signed (7 downto 0); : out signed (15 downto 0) architecture rtl of signed_mult is begin result <= a * b; end rtl; 65 MS EMBEDDED SYSTEMS

Mux2to1 Wait on entity muxcase21waiton is port ( MuxSelect : in bit; In_0, In_1 : in bit ; MuxOut : out bit ) ; end; architecture arch of muxcase21waiton is begin process is begin case MuxSelect is when '0' => MuxOut MuxOut <= In_1 ; wait on muxselect,in_1; end case ; end process; end arch; 66 MS EMBEDDED SYSTEMS

Factorial of a number library ieee; use ieee.std_logic_1164.all; entity factorial is port (num: in integer range 0 to 10; fact:out integer); end; architecture factorial of factorial is begin process(num) variable fac : integer; variable t:integer; begin fac:=1; 67 MS EMBEDDED SYSTEMS

Factorial of a number t := num; while(t/=1) loop fac :=fac*t; t:=t-1; end loop; fact<=fac; end process; end factorial; 68 MS EMBEDDED SYSTEMS