Readout controller Block Diagram S. Hansen - CD-1 Lehman Review1 VXO Ø Det Links to 24 SiPM Front End Boards Clock Event Data USB ARM uC A D Rd Wrt 100Mbit Ethernet Network Interface FPGA 48V Power From Bulk Supply LV DC-DC Converters 3.3v 1.8v 1.2v LP DDR RAM D A Triggers Control Status LPF Optical Link To DAQ System Optical Link To Another Controller (optional)

Octal UltraSound Processor Octal UltraSound Processor FPGA FR Clk Bias Bus Bias Trim DAC 1 of 4 SiPMs One of 8 12 bit 80msps ADCs/chip Cvt Clk Counter Mother Board S Dat One of 64 Channels 500MB LPDDR RAM Parallel FLASH CFG ROM Chan0..15 Chan Chan Chan Link to readout Controller LV DC-DC Converters 3.3v 1.8v 1.2v Bias Bus SiPM Bias Generator 48V ARM Microcontroller with ECC RAM USB 2.5v

Front End Device Options Present (unofficial) default: VMM2: Pros: Rad tolerant by design. Low power <10mW/ch, low readout bandwidth, (too) high density - 64 channels Not designed for SiPMs. Sensitivity too high (2fc/mV), shaping time too long. – poor double pulse timing Cons: Long overload recovery time, too long even for CMS – fixed in the next iteration. Address long shaping times by halving channel density and ping-ponging between two inputs. TDC+ADC. Serial data rate (400mbit/s) allows the use of flash a based FPGA with built in processor with ECC memory for radiation tolerance. Inherent zero-suppression Allows for relatively small DRAM buffer (512MB) Use peak finder to switch input. Worry – adding a feature not needed by primary customer 10 Bit amplitude ADC one bit shy of desirable dynamic range Relevant Operating Environment Numbers: Channel count Radiation dose – 1E11 neutron/cm2, 1 Krad - in the hottest region Ambient magnetic field 100mT Peak rate per SiPM 700KHz, average rate 130KHz Nominal SiPM gain – 1E6, Zero-suppression threshold – 7p.e. Largest expected signal – 200 p.e. Flash gate to lower voltage for ~500ns of every 1596 ns – delivers very large signal to front end

Front End Device Options, cont’d Third option: QIE11: Pros: Rad tolerant by design. Specifically designed for SiPMs. ADC+TDC. Very large dynamic range, much more than we need. 53MHz sampling should give OK double pulse resolution. Cons: High power - 300mW per channel. Low density (one channel per chip). Input scheme TDR default: Commercial Ultrasound chip : Reasonable power (120mW/ch). Fast sampling (12.5ns) – OK double pulse resolution. 12 bit ADC. Pros: Cons: Unknown radiation tolerance – must be tested. Very high bandwidth data connection (960 Mbit/s) Must use SRAM FPGAs, monitor and refresh FPGA configuration RAM. Use external Must monitor and refresh setup registers in case of SEUs. Cannot use flash based FPGA. ARM R4 processor which has high-rel features, use for rad tolerance. OK density (8 channels/chip) Good overload recovery behavior Low readout data rate (106mbit/s) allows the use of flash based FPGA. requires two input transmission lines. Doubles our CMB to FEB signal paths. Good overload recovery for one polarity of signal, poor for the other. Parallel readout, many pins – 576 LVDS pairs for 64channels Flash gate is bi-polar transient

Short term plans Buy an ultrasound demo board and do radiation tests. If it fails, one less decision to make Keep working on those portions of the front board that are independent of the input device. Understand the VMM2 chip in greater detail. Will need to talk with chip designer