The Technology Catalyst

Performance: Computational capability – Improve application performance by as much as 10X, Increase density and lowering cost (perf/watt & perf/meter2) Versatility Programmability: Reduce the time to develop, operate, and maintain HPC application solutions. Portability: HPC application software that is independent of specific hardware and software architectures. Ease of deployment: Continue operating in the presence of localized hardware failure, contain the impact of software defects, and minimize the likelihood of operator error. HPC customers look out for

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 4 ? Parallel Programming Challenge Ease of Use and Flexibility Irregular Patterns, Data Structures, and Serial Algorithms Scale to Multi-Core Today → Hard Scale to Many-Core Tomorrow → Harder Increasing Cores (2→64+ Cores) Vector Instructions (4→8+ Wide) Cache and Interconnect Latency

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 5 The Technical Computing Architecture Optimizing the Time From Idea to Reality With a New Generation of Intelligent Processors Innovation and Discovery Create Visualize Simulate Technical Computing CAE/CFDWeather DCCLife Science EnergyFinance Analyze

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 6 Insatiable Demand for Performance, Density, and Efficiency Intel Power Reduction Over TimeYour Demand For Performance E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00 1 PFlops 1 TFlops 1 GFlops 100 MFlops 100 PFlops 1 EFlops ZFlops 2029 Source: Top500.org ~ 1 Million Factor Reduction In Energy per Transistor Over 30+ Years

Data Center Convergence Network Storage Compute

Product Line Descriptions, till 2010 & Till & beyond Intel® Itanium® processor 9000 sequence platforms Intel® Xeon® processor 7000 sequence platforms Intel® Xeon® processor 3000 sequence platforms Intel® Xeon® processor 5000 sequence platforms Intel® Itanium® processor 9000 sequence platforms Intel® Xeon® processor E7 platforms Intel® Xeon® processor E3 platforms Intel® Xeon® processor E5 platforms

Intel Processor Product Launch Roadmap Desktop & Mobile Server Atom Workstation *including workstation Tier 1 Q1’11Q4’11Q2’11Q3’11 Intel Atom (Cedarview) Intel Xeon e5 (Romley) Intel Xeon e3 (Bromolow) Intel Xeon e7 (Westmere EX) Intel Xeon e5 (Romley) Tier 1 2nd Gen Intel Core (Sandy Bridge) Intel Xeon e3 (Bromolow)

2011 Xeon CPU Numbering Product line & key CPU attributes encoded to encourage sell-up … E# # Product Line Max CPUs in a node # Skt/Segm Designator # SKU v# Version - Example E7 – v2 Prod Line Brand Version Prod Family Intel® Xeon® Processor E7 – v2 Capability DesignatorActual Socket 8LS (Westmere EX) 6R (Sandy Bridge) 4B2 (Sandy Bridge) 2H2 (Sandy Bridge)

Product Family Progression (hypothetical) Product Family consistency across versions Note: Above does not represent schedule, represents product family number construct only. E E E E E E E E E v2 E v2 E v2 E v2 E v2 E v2 E v2 E v2 E v3 E v3 E v3 E v3 E v3 E v3 E v3 E v3 v4v3v2 Ivy Bridge Future Westmere EX & Sandy Bridge E7 (EX) E5 (EP) E3 (EN) E5-1600E v2E v3

INTEL CONFIDENTIAL 12 More Secure More Efficient More Options Higher performance Lower platform power1 Intel® Turbo Boost Technology 2.0 Improved Platform Power Management Capabilities More Intelligent Intel AES-NI improvements More robust Intel TXT solutions Optimized platforms for:  Performance  Smaller Form Factors  Best value Sandy Bridge Server Platform Summary New micro-architecture on the 32nm process technology 1 Lower platform power claim based on a Xeon® 5600 CPU and Sandy Bridge-EP CPU with the same TDP specification and comparable platform configurations. Platform power reduction is primarily attributed to TDP reduction from a two-chip solution based on the Intel 5520 chip set and ICH-10R, down to a one-chip south bridge solution(Patsburg chip) on the Sandy Bridge platform. Platform Features Up to 8 Cores Sandy Bridge-EP QPI Up to 8 cores, 20 MB cache New Intel® Advanced Vector Extensions Intel® Turbo Boost Technology 2.0 Up to 2 QPI links between CPUs Integrated PCI Express Up to 40 lanes per socket Up to 4 channels DDR memory

INTEL CONFIDENTIAL 13 Xeon ® E5 Platform Roadmap 13 *For a full list of technologies, see WW45 NDA Data Center Group Roadmap on SMCR.Intel.com Intel® Xeon® Processor E Product Family (Sandy Bridge-EX) Four Socket Intel® Xeon® Processor E Product Family (Sandy Bridge-EP) Intel® C600 Series Chipset (Patsburg PCH) Intel® Xeon® Processor E Product Family Intel® C600 Series Chipset Intel® Xeon® Processor 5600 Series (Westmere-EP) Intel® Xeon® Processor 5500 Series (Nehalem-EP) Intel® 5520 Chipset Tylersburg-EPTylersburg-EP Efficient Performance Two Socket Intel® Xeon® Processor 5500 and 5600 Series (Westmere-EP) Intel® 5500 Chipset Tylersburg-EN PlatformTylersburg-EN Platform Value Two Socket Romley-EP 2S Romley-EN 2SRomley-EN 2S Romley-EP 4S Q4'11Q1'11Q2’11Q3’11Q1’12 One &

INTEL CONFIDENTIAL 14 Xeon® 2S Platform Comparison Romley Platform Sandy Bridge (SNB) Architecture  Up to 24 DIMMs  Up to 80 PCIe 2.0 lanes  Two QPI links between CPUs  One-chip (PCH) Sandy Bridge Core Sandy Bridge Core DDR3 x8x4 QPI Xeon® 5500 / 5600 Platform Xeon® 5500 Xeon® 5600 Core Xeon® 5500 Xeon® 5600 Core DDR3 x4 QPI Intel C600 Series (PCH) Serial Attached SCSI (SAS) 4 ports, 6Gb/s up to DDR up to 6.4 GT/s Intel 5500 Series (IOH) Intel ICH 10 QPI up to 36 lanes PCIe2 up to DDR up to 8.0 GT/s up to 40 lanes PCIe3 per socket  Up to 18 DIMMs per 2S platform  Up to 36 PCIe2 lanes  Two-chip IOH / ICH

INTEL CONFIDENTIAL 15 Click to edit the outline text format Second Outline Level  Third Outline Level Fourth Outline Level  Fifth Outline Level  Sixth Outline Level  Seventh Outline Level  Eighth Outline Level Ninth Outline LevelClick to edit Master text styles Second level Third level – Fourth level – Fifth level Romley EP (Socket R) vs. Romley EN (Socket B2) Feature Intel® Xeon® processor E product family Intel® Xeon® processor E product family Comments SocketSocket R (LGA2011)Socket B2 (LGA1356) QPI Ports20-12x CPU-CPU bandwidth on EP Memory Channels*86 EP has 33% higher memory bandwidth DIMM Slots*2412 2x DIMM slots on EP allows more flexible memory configurations Max Memory* (GB) X more memory possible on EP PCIe Lanes* / Controllers* 80 / 2048 / 12 66% more PCIe lanes, EP better suited for systems requiring high I/O connectivity & bandwidth TDP (W) 150 (Wkstn only), 135, 130, 115, 95, 80, LV (Low Power) 95, 80, LV (Low Power) 135W top bin TDP delivers ~20% higher performance over 95W Server vs. Workstation usage Server and WorkstationServer EN primarily targeted for Entry 2S and Premium 1S servers – not recommended for Workstations Application  Mainstream 2S, Blade Serv.  Storage Server  Mainstream 2S / 1S Wkstn.  HPC Platforms  Value 2S & Blade Server  Premium 1S & Blade Server Expect EN baseboard BOM cost ~$50 lower than EP DDR3 E DDR3 QPI E DDR3 x8 x4 E QPI x8 E DDR3 * Per 2S platform EP = Best Performance, Max Memory & I/O Connectivity EN = Cost Optimized, Smaller Form Factor

INTEL CONFIDENTIAL 16 Intel® Advanced Vector Extensions (Intel® AVX) Extension to 128-bit SSE Instruction Support for 256-bit wide vectors and SIMD register set Targets floating point operations Benefits these applications: Engineering Visual processing/recognition Data-mining Physics, Cryptography YMM0 XMM0 128 bits 256 bits (AVX) Programming reference, development emulator, code analyzer, C++ compilers, white papers and forums. 2X the throughput!

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 17 Intel Technology is Changing HPC TCO, Performance, Reliability Extreme Performance Power Efficient Reduce System Cost Increased Reliability 10GbESolid State Disk €Intel IT evaluation results. Optimize Performance for I/O Intensive Apps and Boot Drive Replacement Bridging the Gap Between 1GbE and Infiniband®

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 18 Scaling Performance Forward One Development Environment – Multi- to Many-core Simplify Your Development Performance Optimize/Tune Performance Optimize/Tune Confidence Correctness Insight Architectural Analysis

*Other names and brands may be claimed as the property of others. Copyright © 2009, Intel Corporation. 19 Solving Your HPC Challenges – Certified cluster configurations to simplify cluster deployment – Use Intel® Cluster Checker to validate configurations: ensure a highly reliable solution – Easily optimize application performance and eliminate the need to increase software resources – Develop highly portable, parallel software – Up to 3x performance gains to decrease your time to discovery – Improved power technology, more efficient data for a lower TCO Intelligent Performance Software Versatility Ease of Deployment Scaling Performance Forward For notes and disclaimers, see legal information slide at end of this presentation.

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