Sampling Theory ADC Types EE174 – SJSU Tan Nguyen

Shannon Sampling Theorem

Analog sinusoid x(t) = A cos(2πf 0 t +  ) Sample at T s = 1/f s x[n] = x(T s n) = A cos(2π f 0 T s n +  ) Keeping the sampling period same, sample y(t) = A cos(2 π(f 0 + kf s )t +  ) where k is an integer y[n]= y(T s n) = A cos(2π (f 0 + kf s )T s n +  ) = A cos(2πf 0 T s n + 2πkf s T s n +  ) = A cos(2πf 0 T s n + 2πk n +  ) = A cos(2πf 0 T s n +  ) = x[n] Here, f s T s = 1 Since k is an integer, cos(x ± 2πk) = cos(x) y[n] indistinguishable from x[n]  Frequencies f 0 + k f s for k  0 are aliases of frequency f 0 Aliasing

Sampling Theorem A sinusoid signal of 90 cycle/second is sampled at f s = 1000 samples/second. The wave has a frequency of 0.09 of the sampling rate: f = 0.09 x f s = 0.09 x 1000 = 90 Hz. Equivalently, there are 1000/90 = 11.1 samples taken over a complete cycle of the sinusoid.  This is proper sampling since the samples represent accurately the sinusoid because there is no other sinusoid that can produce the same samples. Noe, if sampling f s = 95 samples/second f = 0.95 x f s or there are 1.05 samples per sin wave cycle. Clearly, this is an improper sampling of the signal because another sine wave can produce the same samples. The original sine misrepresents itself as another sine. This phenomenon is called aliasing.

Given x(t) = A cos(ωt + φ) to be sampling at equal space T s. x[n] = x(nT s ) = A cos(ωnT s + φ) = A cos( ώn + φ) Defined new frequency variable ώ known as the discrete-time frequency or normalized continuous-time frequency: ώ ≡ ωT s = ω / f s Consider x(t) = 2 sin(2  x90t) at sampling rates of 1000 and 95 samples per second Discrete frequencies: ώ 1000 = 2π x 90 / 1000 = 0.18π ώ 95 = 2π x 90 / 95 = 1.9π x 1000 [n] = sin[0.18πn]  - π < 0.18 π < π x 95 [n] = sin[1.9πn] = sin[(- 0.1π + 2π)n] = sin[- 0.1πn] = - sin[0.1πn]  as expected since sinusoid is periodic with 2π For 1000 Hz sampling rate  ω = ώf s = 0.18π x 1000 = 180 π = 2π x 90  recover original signal with f = 90Hz Similarly, for 95 Hz sampling rate  ω = ώf s = 0.1π x 95 = 9.5 π = 2π x 4.75  Aliasing signal recover f = 4.75Hz instead of 90Hz Sampling Sinusoidal Signals

Sound is audible in 20 Hz to 20 kHz range: f max = 20 kHz and the Nyquist rate 2 f max = 40 kHz What is the extra 10% of the bandwidth used? Rolloff from passband to stopband in the magnitude response of the anti-aliasing filter 44 kHz makes sense. Why 44.1 kHz? At the time the choice was made, only recorders capable of storing such high rates were VCRs. NTSC: 490 lines/frame, 3 samples/line, 30 frames/s = samples/s PAL: 588 lines/frame, 3 samples/line, 25 frames/s = samples/s CD-ROM Mode 1 = 2,048 bytes/block, CD-ROM Mode 2 = 2,336/bytes/block, CD data transfer rate of 75 blocks per second by 60 seconds by the minute size of disc. For example, a 80 minute disc written in CD-ROM Mode 1 format: Total CD storage space = 2048 bytes/block x 75 blocks/second x 60 seconds x 80 minutes = 737,280,000 bytes or 800MB. Why 44.1 kHz for Audio CDs?

Types of ADC Flash ADC Successive approximation converter Counter Ramp Converter Integrating ADC

Flash ADC 3-bit flash ADC Also known as Parallel ADC A n-bit flash ADC uses 2 n-1 comparators and a priority encoder logic. Advantage: the fastest type of ADC. Disadvantages: limited resolution, expensive, large power consumption and low accuracy. Applications: Data acquisition, satellite communication, radar processing, sampling oscilloscope and high density disk drives

Flash ADC Example Let V ref = 8V and V in = 5.25V, what is the digital output code? Solution: For V in = 5.25V. The output of comparators are:  Output of Priority Encoder = 101 LSB Let V ref = 16V and V in = 5.25V, what is the digital out put code? Solution: For V in = 5.25V. The output of comparators are:  Output of Priority Encoder = 010 LSB 5.25V

Successive-approximation ADC Start Conversion (SC) A DAC is used to generate approximations of the input voltage. A comparator is used to compare V in and V appr. In each cycle, SAR finds one output bit using comparator. To start conversion, set SC = 1. When conversion ends, EOC = 1. Quite fast, expensive, high accuracy and one of the most widely used design for ADCs.

Successive Approximation ADC Example Given: 8-bit ADC, V in = 5.65V and V full scale = 8V. Find digital value V in Start MSB (Bit 7)  LSB (Bit 0): Let Bit 7 = 1  V DAC = 4V < 5.65  Bit 7 = 1 Bit 6 = 1  V DAC = (4 + 2)V = 6V > 5.65  Bit 6 = 0 Bit 5 = 1  V DAC = (4 + 1)V = 5V < 5.65  Bit 5 = 1 Bit 4 = 1  V DAC = ( )V = 5.5V < 5.65  Bit 4 = 1 Bit 3 = 1  V DAC = ( )V = 5.75V > 5.65  Bit 3 = 0 Bit 2 = 1  V DAC = ( )V = 5.625V < 5.65  Bit 2 = 1 Bit 1 = 1  V DAC = ( )V = V > 5.65  Bit 1= 0 Bit 0 = 1  V DAC = ( )V = V > 5.65  Bit 0 = 0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 = 5.65V V DAC

Counter Ramp Converter Counter-ramp converters comprise a D-A converter, a single comparator, a counter, a clock and control logic Counter is initially reset to zero. The sample-and-hold amplifier is use to freeze the analogue voltage available for an extended period. A clock signal increments the counter that feeds to ADC to generate the reference voltage to compare with the analogue input. When DAC reference voltage > analog input  comparator output = 1, which notifies the control logic the conversion has finished encoder input signal digital output The value of the counter is output as the digital value. A drawback of the counter-ramp converter is the length of time required to convert large voltages. A 10 bit ADC will require 1024 iterations to resolve the maximum input voltage. The worst case must be assumed when calculating conversion times

Counter Ramp Converter V in =5.6V V ref = 8 V

Integrating ADC Speed: Low Cost: Low Accuracy: High The simplest form of an integrating ADC uses a single-slope architecture. Here, an unknown input voltage is integrated and the value compared against a known reference value. The time it takes for the integrator to trip the comparator is proportional to the unknown voltage (T INT /V IN ). In this case, the known reference voltage must be stable and accurate to guarantee the accuracy of the measurement. Single-Slope ADC Architecture

In dual slope type ADC, the integrator generates two different ramps, one with the known analog input voltage VA and another with a known reference voltage – Vref. Hence it is called as dual slope A to D converter. VSVS Dual-Slope ADC Architecture

Dual-Slope ADC ArchitectureC

TYPESPEED (RELATIVE)COST (RELATIVE) FlashVery FastHigh Successive ApproximateMedium FastLow Counter RampSlowLow Dual SlopeSlowMedium ADC Summary

References: 1. Understanding Data Converters – SLAA ADS8318 data sheet – SLAS568A Evaluating High Speed DAC Performance by Walt Kester – Analog Devices MT-013 Tutorial HomeHome > Products and Services > White Papers > Understanding Resolution in High-Speed Digitizers/OscilloscopesProducts and ServicesWhite Papers ume.gatech.edu/mechatronics_course/ADC_F10.pptx