CSE477 L08 Capacitance.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 08: MOS & Wire Capacitances Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L08 Capacitance.2Irwin&Vijay, PSU, 2003 Review: Delay Definitions t V out V in input waveform output waveform t p = (t pHL + t pLH )/2 Propagation delay t 50% t pHL 50% t pLH tftf 90% 10% trtr signal slopes V in V out

CSE477 L08 Capacitance.3Irwin&Vijay, PSU, 2003 CMOS Inverter: Dynamic V DD RnRn V out = 0 V in = V DD CLCL t pHL = f(R n, C L ) Today’s focus Next lecture’s focus  Transient, or dynamic, response determines the maximum speed at which a device can be operated.

CSE477 L08 Capacitance.4Irwin&Vijay, PSU, 2003 Sources of Capacitance CwCw C DB2 C DB1 C GD12 C G4 C G3 wiring (interconnect) capacitance intrinsic MOS transistor capacitances V out2 V in extrinsic MOS transistor (fanout) capacitances V out V in M2M2 M1M1 M4M4 M3M3 V out2 CLCL ndrain pdrain

CSE477 L08 Capacitance.5Irwin&Vijay, PSU, 2003 Intrinsic MOS Capacitances  Structure capacitances  Channel capacitances  Diffusion capacitances from the depletion regions of the reverse-biased pn-junctions C GS C SB C DB C GD C GB S G B D C GS = C GCS + C GSO C GD = C GCD + C GDO C GB = C GCB C SB = C Sdiff C DB = C Ddiff

CSE477 L08 Capacitance.6Irwin&Vijay, PSU, 2003 MOS Structure Capacitances xdxd Source n+ Drain n+ W L drawn xdxd Poly Gate n+ t ox L eff Top view lateral diffusion C GSO = C GDO = C ox x d W = C o W Overlap capacitance (linear)

CSE477 L08 Capacitance.7Irwin&Vijay, PSU, 2003 MOS Channel Capacitances S D p substrate B G V GS + - n+ depletion region n channel C GS = C GCS + C GSO C GD = C GCD + C GDO C GB = C GCB  The gate-to-channel capacitance depends upon the operating region and the terminal voltages

CSE477 L08 Capacitance.8Irwin&Vijay, PSU, 2003 Review: Summary of MOS Operating Regions  Cutoff (really subthreshold) V GS  V T l Exponential in V GS with linear V DS dependence I D = I S e (qV GS /nkT) (1 - e - (qV DS /kT) ) (1 - V DS ) where n  1  Strong Inversion V GS > V T l Linear (Resistive) V DS < V DSAT = V GS - V T I D = k’ W/L [(V GS – V T )V DS – V DS 2 /2] (1+ V DS )  (V DS ) l Saturated (Constant Current) V DS  V DSAT = V GS - V T I DSat = k’ W/L [(V GS – V T )V DSAT – V DSAT 2 /2] (1+ V DS )  (V DS ) V T0 (V)  (V 0.5 ) V DSAT (V)k’(A/V 2 ) (V -1 ) NMOS x PMOS x

CSE477 L08 Capacitance.9Irwin&Vijay, PSU, 2003 Average Distribution of Channel Capacitance Operation Region C GCB C GCS C GCD C GC CGCG CutoffC ox WL00 C ox WL + 2C o W Linear (Resistive) 0C ox WL/2 C ox WLC ox WL + 2C o W Saturation0(2/3)C ox WL0 (2/3)C ox WL + 2C o W l Channel capacitance components are nonlinear and vary with operating voltage l Most important regions are cutoff and saturation since that is where the device spends most of its time

CSE477 L08 Capacitance.10Irwin&Vijay, PSU, 2003 MOS Diffusion Capacitances S D p substrate B G V GS + - n+ depletion region n channel C SB = C Sdiff C DB = C Ddiff  The junction (or diffusion) capacitance is from the reverse-biased source-body and drain-body pn-junctions.

CSE477 L08 Capacitance.11Irwin&Vijay, PSU, 2003 Source Junction View side walls channel W xjxj channel-stop implant (N A +) source bottom plate (N D ) LSLS substrate (N A ) C diff = C bp + C sw = C j AREA + C jsw PERIMETER = C j L S W + C jsw (2L S + W) junction depth

CSE477 L08 Capacitance.12Irwin&Vijay, PSU, 2003 Review: Reverse Bias Diode  All diodes in MOS digital circuits are reverse biased; the dynamic response of the diode is determined by depletion-region charge or junction capacitance C j = C j0 /((1 – V D )/  0 ) m where C j0 is the capacitance under zero-bias conditions (a function of physical parameters),  0 is the built-in potential (a function of physical parameters and temperature) and m is the grading coefficient l m = ½ for an abrupt junction (transition from n to p-material is instantaneous) l m = 1/3 for a linear (or graded) junction (transition is gradual)  Nonlinear dependence (that decreases with increasing reverse bias) + - VDVD

CSE477 L08 Capacitance.13Irwin&Vijay, PSU, 2003 Reverse-Bias Diode Junction Capacitance V D (V) C j (fF) linear (m=1/3) abrupt (m=1/2) C j0

CSE477 L08 Capacitance.14Irwin&Vijay, PSU, 2003 Transistor Capacitance Values for 0.25  C ox (fF/  m 2 ) C o (fF/  m) C j (fF/  m 2 ) mjmj  b (V) C jsw (fF/  m) m jsw  bsw (V) NMOS PMOS Example: For an NMOS with L = 0.24  m, W = 0.36  m, L D = L S =  m C GC = C ox WL = C GSO = C GDO = C ox x d W = C o W = so C gate_cap = C ox WL + 2C o W = C bp = C j L S W = C sw = C jsw (2L S + W) = so C diffusion_cap =

CSE477 L08 Capacitance.15Irwin&Vijay, PSU, 2003 Transistor Capacitance Values for 0.25  C ox (fF/  m 2 ) C o (fF/  m) C j (fF/  m 2 ) mjmj  b (V) C jsw (fF/  m) m jsw  bsw (V) NMOS PMOS Example: For an NMOS with L = 0.24  m, W = 0.36  m, L D = L S =  m C GC = C ox WL = 0.52 fF C GSO = C GDO = C ox x d W = C o W = 0.11 fF so C gate_cap = C ox WL + 2C o W = 0.74 fF C bp = C j L S W = 0.45 fF C sw = C jsw (2L S + W) = 0.45 fF so C diffusion_cap = 0.90 fF

CSE477 L08 Capacitance.16Irwin&Vijay, PSU, 2003 Review: Sources of Capacitance V out CwCw V in C DB2 C DB1 C GD12 M2M2 M1M1 M4M4 M3M3 V out2 C G4 C G3 wiring (interconnect) capacitance intrinsic MOS transistor capacitances V out2 V in extrinsic MOS transistor (fanout) capacitances V out CLCL ndrain pdrain

CSE477 L08 Capacitance.17Irwin&Vijay, PSU, 2003 Gate-Drain Capacitance: The Miller Effect  Miller Effect: A capacitor experiencing identical but opposite voltage swings at both its terminals can be replaced by a capacitor to ground whose value is two times the original value. V in C GD1 M1M1 V out VV VV V in M1M1 V out VV VV 2C GB1  M1 and M2 are either in cut-off or in saturation.  The floating gate-drain capacitor is replaced by a capacitance-to-ground (gate-bulk capacitor).

CSE477 L08 Capacitance.18Irwin&Vijay, PSU, 2003 Drain-Bulk Capacitance: K eq ’s (for 2.5  m) high-to-lowlow-to-high K eqbp K eqsw K eqbp K eqsw NMOS PMOS  We can simplify the diffusion capacitance calculations even further by using a K eq to relate the linearized capacitor to the value of the junction capacitance under zero-bias C eq = K eq C j0

CSE477 L08 Capacitance.19Irwin&Vijay, PSU, 2003 Extrinsic (Fan-Out) Capacitance  The extrinsic, or fan-out, capacitance is the total gate capacitance of the loading gates M3 and M4. C fan-out = C gate (NMOS) + C gate (PMOS) = (C GSOn + C GDOn + W n L n C ox ) + (C GSOp + C GDOp + W p L p C ox )  Simplification of the actual situation l Assumes all the components of C gate are between V out and GND (or V DD ) l Assumes the channel capacitances of the loading gates are constant

CSE477 L08 Capacitance.20Irwin&Vijay, PSU, 2003 Layout of Two Chained Inverters In Out Metal1 V DD GND 1.2  m = / /0.25 PMOS NMOS Polysilicon W/LAD (  m 2 ) PD (  m) AS (  m 2 ) PS (  m) NMOS0.375/ PMOS1.125/

CSE477 L08 Capacitance.21Irwin&Vijay, PSU, 2003 Components of C L (0.25  m) C Term ExpressionValue (fF) H  L Value (fF) L  H C GD1 2 C o n W n 0.23 C GD2 2 C o p W p 0.61 C DB1 K eqbpn AD n C j + K eqswn PD n C jsw C DB2 K eqbpp AD p C j + K eqswp PD p C jsw C G3 (2 C on )W n + C ox W n L n 0.76 C G4 (2 C op )W p + C ox W p L p 2.28 CwCw from extraction0.12 CLCL 

CSE477 L08 Capacitance.22Irwin&Vijay, PSU, 2003 Wiring Capacitance  The wiring capacitance depends upon the length and width of the connecting wires and is a function of the fan-out from the driving gate and the number of fan-out gates.  Wiring capacitance is growing in importance with the scaling of technology.

CSE477 L08 Capacitance.23Irwin&Vijay, PSU, 2003 Parallel Plate Wiring Capacitance electrical field lines W H t di dielectric (SiO 2 ) substrate C pp = (  di /t di ) WL current flow permittivity constant (SiO 2 = 3.9) L

CSE477 L08 Capacitance.24Irwin&Vijay, PSU, 2003 Permittivity Values of Some Dielectrics Material  di Free space1 Teflon AF2.1 Aromatic thermosets (SiLK)2.6 – 2.8 Polyimides (organic)3.1 – 3.4 Fluorosilicate glass (FSG)3.2 – 4.0 Silicon dioxide3.9 – 4.5 Glass epoxy (PCBs)5 Silicon nitride7.5 Alumina (package)9.5 Silicon11.7 Hafnium dioxide22

CSE477 L08 Capacitance.25Irwin&Vijay, PSU, 2003 Sources of Interwire Capacitance interwire fringe pp C wire = C pp + C fringe + C interwire = (  di /t di )WL + (2  di )/log(t di /H) + (  di /t di )HL

CSE477 L08 Capacitance.26Irwin&Vijay, PSU, 2003 Impact of Fringe Capacitance H/t di = 1 H/t di = 0.5 C pp W/t di

CSE477 L08 Capacitance.27Irwin&Vijay, PSU, 2003 Impact of Interwire Capacitance

CSE477 L08 Capacitance.28Irwin&Vijay, PSU, 2003 Wiring Insights  For W/H < 1.5, the fringe component dominates the parallel-plate component. Fringing capacitance can increase the overall capacitance by a factor of 10 or more.  When W/H < 1.75 interwire capacitance starts to dominate  Interwire capacitance is more pronounced for wires in the higher interconnect layers (further from the substrate)  Rules of thumb l Never run wires in diffusion l Use poly only for short runs l Shorter wires – lower R and C l Thinner wires – lower C but higher R  Wire delay nearly proportional to L 2

CSE477 L08 Capacitance.29Irwin&Vijay, PSU, 2003 Wiring Capacitances FieldActivePolyAl1Al2Al3Al4 Poly88 54 Al Al Al Al Al fringe in aF/  m pp in aF/  m 2 PolyAl1Al2Al3Al4Al5 Interwire Cap per unit wire length in aF/  m for minimally-spaced wires

CSE477 L08 Capacitance.30Irwin&Vijay, PSU, 2003 Dealing with Capacitance  Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO 2 l family of materials that are low-k dielectrics l must also be suitable thermally and mechanically and l compatible with (copper) interconnect  Copper interconnect allows wires to be thinner without increasing their resistance, thereby decreasing interwire capacitance  SOI (silicon on insulator) to reduce junction capacitance

CSE477 L08 Capacitance.31Irwin&Vijay, PSU, 2003 Next Time: Dealing with Resistance  MOS structure resistance - R on  Wiring resistance  Contact resistance

CSE477 L08 Capacitance.32Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next lecture l MOS resistance -Reading assignment – Rabaey, et al, 4.3.2, Another lecture given by guest lecturer Greg Link  Reminders l HW#2 due today l Project specs due (on-line) October 9 th l HW#3 due October 16 th l HW#4 due November 11 th (not Nov 4 th as on outline) l HW#5 will be optional (due November 20 th ) l Evening midterm exam scheduled -Monday, October 20 th, 20:15 to 22:15, Location TBD -Only one midterm conflict scheduled