Digital Logic & Design Dr.Waseem Ikram Lecture 44

Recap Memory Requirement is large Memory Implemented small Standard data unit size Standard number of memory locations Base address of memory Memory Map 1 MB memory map Divided into 16, 64K blocks ROM, Data, Program, Stack 12, 64K vacant blocks for expansion

Block diagram of a Logic Element

LUT programmed to generate a function Address InputData Output ABCF

LUT Programmed as Full-Adder Address InputData Output ABC in SumC out

Continuous signal showing temperature varying with time

Sampling the Continuous Signal at 15 equal intervals

Reconstructed Signal by plotting 15 sampled values

Reconstructed Signal by plotting 7 sampled values

Sample and Hold Circuit

Analogue Signal

Sample & Hold Signal

Digitized Signal

Analogue Signal

Sample & Hold Signal

Digitized Signal

Op-Amp

Op-Amp as an Inverting Amplifier

Op-Amp as a Comparator

Flash A/D Converter +V RE F R R R R R R R R Input from sample and hold circuit Op-Amp Comparators Priority Encoder Parallel Binary Output Enable

3-bit FLASH A/D Converter +V REF =8 R R R R R R R R Op-Amp Comparators Priority Encoder Parallel Binary Output Enable 7 volts 6 volts 5 volts 4 volts 3 volts 2 volts 1 volts 4.2 volts

Input analogue voltage samples

Binary output representing input analogue voltage samples

Dual-Slope A/D Converter

Recap Expanding Data Unit size Expanding Locations Expanding Data unit size and locations Address Decoders Accessing memory at specified base address Logic gate decoders n x m gate decoders

Operation of Dual-Slope A/D Converter Time interval t Input signalOutput of Integrator Output of Comparator Clock InputCounter 0V in -V1enabledCounting 1V in -V1enabledCounting nV in -V1enabledTerminal count reached. Counter reset. Switched to –V ref n+1-V ref -V1enabledCounting n+2-V ref -V1enabledCounting n+m-V ref 00disabledBinary value representing V analogue

Recap Field Programmable Logic Array Logic blocks Generate logic functions by programming LUT Row & Col programmable interconnects I/O programmable blocks

FPGAs Logic Block Multiple Logic Elements (fig 1) LUT, flip-flop, cascade logic Control logic, programmable selects

Programming LUTs Implementing function by Programming LUT Example 1 (tab 1a) Example 2 full adder (tab 1b) Programming Row & Column interconnects through transistor switches.

Analogue to Digital & Digital to Analogue Converters Conversion of real world quantities Mobile phones Digital Thermometers Digital storage of sound and pictures Digital voltmeters Industrial control and monitoring.

Analogue to Digital Sampling (fig 2a-d) Under-sampling Over-sampling Sampling frequency Nyquist frequency Holding Sampled value Sample and Hold Circuit (fig 3a-b)

Quantization Quantization (fig 4, 5)) Process of converting analogue value to a code Few bits, quantization levels less accurate More bits, quantization levels more accurate

Operational Amplifier Linear Amplifier (fig 6a) Inverting/Non-inverting inputs Single outputs High input impedance Low output impedance Very High voltage gain Inverting Amplifier (fig 6b) Comparator (fig 6c)

FLASH Converter Fast conversion time Expensive circuit complexity Resistor voltage divider Multiple Op-Amps as comparators Input signal connected to all comparators Comparator o/p high if i/p higher than ref Priority encoder Encoder o/p is digital equivalent of i/p

FLASH Converter Ckt diagram (fig 7) Input sample values (fig 8) Output digital values (fig 9)

Dual-Slope Converter Slower than FLASH Used in Digital voltmeters and other measuring instruments Ckt. Diagram (fig 10) Working (tab 2)