CSE477 L27 System Interconnect.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 27: System Level Interconnect Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L27 System Interconnect.2Irwin&Vijay, PSU, 2003 The Nature of Interconnect Local Interconnect Global Interconnect From Kang, 87

CSE477 L27 System Interconnect.3Irwin&Vijay, PSU, 2003 Global Interconnect  Classes of global interconnects l System level signal interconnect - buses l Global set and reset lines l System clock(s) l V DD and GND planes  Classes of parasitics l capacitive l resistive l inductive  Impacts of parasitics l Reduced reliability (crosstalk) l Reduced performance

CSE477 L27 System Interconnect.4Irwin&Vijay, PSU, 2003 System Level Signal Interconnect  Many drivers - only one active at a time  Many receivers - many may be active at a time A in B in C in D in W out X out Y out Z out Tristate Bus drivers Bus receivers Bus

CSE477 L27 System Interconnect.5Irwin&Vijay, PSU, 2003 Tristate Buffers InOut !En En InOut En  Three states - 0, 1, and Z (high impedance)  For driving large loads l avoid stacked transistors in the output gate (as in above) since it has to be sized to drive the load (thus stacked transistors would incur a large area overhead) In Out En !En

CSE477 L27 System Interconnect.6Irwin&Vijay, PSU, 2003 Tristate Buffers InOut !En En 0101 !In 1010 Z (disconnected) InOut En  Three states - 0, 1, and Z (high impedance)  For driving large loads l avoid stacked transistors in the output gate (as in above) since it has to be sized to drive the load (thus stacked transistors would incur a large area overhead) In Out En !En 0101 Z 1010 !In

CSE477 L27 System Interconnect.7Irwin&Vijay, PSU, 2003 Reducing Effective Capacitance  Shared resources may also incur extra switching activity impacting the energy consumption A in B in C in D in W out X out Y out Z out D in C in Y out Z out B in A in W out X out

CSE477 L27 System Interconnect.8Irwin&Vijay, PSU, 2003 Driving Large Capacitive Loads  Large fan out on-chip loads can be in the multi-picofarad range; off-chip loads can be as large as 50pF  Design techniques for driving large loads l Appropriately sized transistors in the driving gate l Partitioning drivers into chains of gradually increasing (in size) buffers -when optimizing for performance, the delay of a multi-stage driver should be divided equally over all stages -a fan-out (sizing) factor of 4 (FA4) per stage leads to the minimum delay for contemporary processes l Use better interconnect materials (like copper and low-K dielectrics) l Introduce buffers (buffer (or repeater) insertion) into long wires to reduce the propagation delay

CSE477 L27 System Interconnect.9Irwin&Vijay, PSU, 2003 Impact of Partitioned Drivers Stage W n (  m) W p (  m) PMOS/NMOS ratio of 1.9  For C i of 2.5fF and C L of 20pF, F (overall effective fanout) = 8,000 leading to a 7 stage design with a scaling factor of f = 3.6 and a propagation delay (t p ) of 0.76ns.  Can trade-off performance for area and energy reduction. Setting t p,max to 2ns leads to a 3 stage design, f = 20, and t p = 1.8ns Stage123 W n (  m) W p (  m)  Area savings of 7.5x; delay increased by ~ 2.5x; overall power dissipation reduced by ~24%

CSE477 L27 System Interconnect.10Irwin&Vijay, PSU, 2003 Designing Large Transistors D(rain) S(ource) G(ate)  Long polysilicon wires are highly resistive, degrading performance. So implement a wide transistor with many smaller transistors in parallel. D(rain) S(ource) G(ate) 2 more sections of diffusion

CSE477 L27 System Interconnect.11Irwin&Vijay, PSU, 2003 Impact of Better Interconnect Materials  Use better interconnect materials l As processes shrink, wires get shorter (reducing C) but they get closer together (increasing C) and narrower (increasing R). So RC wire delay increases and capacitive coupling gets worse. -Copper has about 40% lower resistivity than aluminum, so copper wires can be thinner (reducing C) without increasing R l Use silicides (WSi2, TiSi2, PtSi2 and TaSi) -Conductivity is 8-10 times better than poly alone l Low capacitance (low-k) dielectrics (insulators) such as polymide or even air instead of SiO 2 -must also be suitable thermally and mechanically compatible with (copper) interconnect  Only buys one generation!  Drive long poly wires from both ends – or use extra metal bypass wires l providing a bypass line every 16 cells for a poly word line driving 1024 cells in a memory core reduces the WL delay by ~4,000

CSE477 L27 System Interconnect.12Irwin&Vijay, PSU, 2003 Impact of Buffer Insertion  The most popular design approach to reducing the propagation delay of long wires is to introduce intermediate buffers (repeaters) in the interconnect line. l making a wire m times shorter reduces its propagation delay quadratically and is sufficient to offset the extra delay of the repeaters (t pbuf ) when the wire is sufficiently long m opt = L  ((0.38rc)/t pbuf ) =  (t pwireunbuffered /t pbuf ) t p,opt = 2  (t pwireunbuffered t pbuf )  For example, for a 10 cm long, 1  m wide wire and a t pbuf of 0.1ns, partitioning a AL1 wire into 18 sections would give an overall delay time of 3.5 ns (compared to the unbuffered delay of 32.4 ns). For poly the delay reduces to 212 ns (from 112  s) with 1,058 sections and for AL5 to 1.3 ns (from 4.2 ns) with 6 sections  Repeater insertion is an essential tool in combating long wire delays

CSE477 L27 System Interconnect.13Irwin&Vijay, PSU, 2003 Capacitive Coupling (Cross Talk)  Unwanted coupling with adjacent signal wires injects noise into a signal depending on the transient values of the other signals routed in the neighborhood Crosstalk vs. Technology 0.16m CMOS 0.12m CMOS 0.35m CMOS 0.25m CMOS Pulsed Signal Black line quiet Red lines pulsed Glitches strength vs technology From Dunlop, Lucent, 2000

CSE477 L27 System Interconnect.14Irwin&Vijay, PSU, 2003 Dealing with Capacitive Cross Talk  Design Techniques l Avoid floating nodes. Nodes sensitive to cross talk problems (like precharged buses) should be equipped with keeper devices to reduce the impedance l Separate, in the layout, sensitive nodes from full-swing signals l Make the rise (fall) times as large as possible (beware of increases in short circuit power!) l Use differential signaling in sensitive low-swing signals turning cross talk into a common-mode noise source l Keep capacitances between wires small. Don’t run two parallel wires on the same layer at minimum wire pitch for long distances. Run wires on adjacent layers perpendicular to each other. l Provide shielding wires – GND or V DD – between two signals turning the interwire capacitance into a capacitance-to-GND. l Interleave every signal layer with a GND or V DD metal plane. weak

CSE477 L27 System Interconnect.15Irwin&Vijay, PSU, 2003 Shielding to Reduce Cross Talk substrate (GND) shielding layer V dd GND shielding wire signal wire

CSE477 L27 System Interconnect.16Irwin&Vijay, PSU, 2003 Power Distribution Network  Ohmic drops that degrade the signal level are especially important in the power distribution network where current levels can easily reach amperes. Such IR drops l affect reliability l impact the performance as even a small drop in V DD can cause a significant increase in delay  Design techniques for power distribution networks l Reduce the maximum distance between the supply pins and the circuit supply connections by adopting a structured layout of the power distribution network -route power and ground vertically (or horizontally) inter-digitized on the same layer bringing power in from two sides of the die -use two metal layers for power distribution bringing power in from four sides of the die -use two solid metal planes for distribution of V DD and GND l Size the power network appropriately

CSE477 L27 System Interconnect.17Irwin&Vijay, PSU, 2003 Next Lecture and Reminders  Next (!last!) lecture l Design for test – for your reference only -Reading assignment – Rabaey, et al, Design Insert H.1-H.4 l Technology trends and scaling – Greg will guest lecture -Reading assignment – Rabaey, et al, 2.5; 3.5; 4.6; 5.6  Reminders l Final grading negotiations/correction (except for the project prototype/final and the final exam) must be concluded by tomorrow, December 10 th l Final exam scheduled -Tuesday, December 16 th from 10:10 to noon in 118 and 113 Thomas