3.2.2 SRAM Memories – Design and interfacing to 16-bit memories Ex 3.6: functional design of a 16-bit memory CPU: 16-bit data bus, 24-bit address bus, please use n*(64k*8-bit SRAM, has a single chip-select input), to form a 1 Mbytes memory system with the lowest physical addresses beginning 1Mbyte = 64K byte * 16  64K * 16-bit * 8 Even section has 64K byte * 8, odd section has 64K byte *8  use A0 to do the byte enable A1-A16 is used to “word-address” A17-A19 is used to the “row-select” decoder Decoder is only enabled as A20 – A23 is all zero

EX 3.7: using 4K*1 bit SRAM to form 8Kbyte memory system in Intel 80286 16-bit data bus CPU

Design and Interfacing to 32-bit memories Ex 3.8: interfacing a 32-bit memory to Motorola 680x0 32-bit address CPU with 64K*4-bit SRAM to form 1 Mbytes covers the highest 1-Mbyte of the 232=4 Gbyte addressing space 1 Mbyte = (220*8-bit) /(216*4-bit)= 32 (need 32 64k*4-bit SRAM) 32-bit /8-bit = 4 column, each column have 32/4 = 8 SRAM, 2 SRAM to form a 8-bit, 8/2 = 4 rows

Fig. 3. 12 shows the 32-bit data bus to an Intel 80x86 CPU Fig. 3.12 shows the 32-bit data bus to an Intel 80x86 CPU. Each of the four bytes section is made up of one 2K*8 SRAM chip

3.2.3 DRAM memories 8207 DRAM controller Can drive up to 4 banks composed of 256-K bits DRAM chips Dual-port configuration, two internal port interfaces (allows two independent processors to access a single main memory controlled by on 8207 DRAM controller. PEA#, PEB#)

8207 is interfaced to 16K, 64K, and 256K DRAMs using the address connections A0: byte enable A1 and A2 (interleave mode) or A18 and A19 (non-interleave mode) will be applied to the 8207’s bank-select input pins to select one of up to four size of the DRAM

Fig. 3.16 using 8207 DRAM controller to control 256k*1 bit DRAM chip

3.3 Advanced DRAM Access Modes Three advanced burst access modes Page mode Static column Nibble mode All of them are repeated access to the same row without the row access time overhead

Page mode Holding the row address Change the column address to provide faster random access to any of the 1024 column bits on a given row

Static column mode Slightly slower than page mode Used in applications that require less noise than the page mode

Nibble mode Allow access up to three extra bits of data from sequential locations for every row access It has much higher rte than in the other two modes

3.3.5 Example of 32-bit Page/Static Column Design Static column design => memory is divided into page (each page has the same row address) The speed-up occurs (no wait states are required) If consecutive accesses are within the same page (require external hardware interface to detect whether the consecutive address accesses are in same page) When the memory access outside the same page, the system will run with the normal wait state Fig. 3.22 shows the Motorola 68020 (32-bit data bus, 24-bit address line) design Use 1M*1 bit DRAM chips to form 16 Mbyte, 32-bit data bus non-interleaving memory system 32 bit  32 * 1M*1bit DRAM chips per bank  4 Mbyte 16 Mbyte needs 4 banks 32 bits need A0-A1 to do the byte enable for each bank 1 Mbit need 20 address lines (A2-A21) to do the address space 4-bank requires 2 address line to do bank selection (A22-A23)

SN74ALS6310 is a static column detect circuit, which receives the page number (A21-A12) and compares two successive row addresses to check for a match