Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation.

Slides:

Advertisements

Similar presentations

Ischia, giugno 2006Riunione Annuale GE 2006 Università di Catania Facoltà di Ingegneria DIEES Catania - ITALY STMicroelectronics Catania site Lumped.

Advertisements

Rama Arora, Physics Department PGGCG-11, Chandigarh

B. BOUDJELIDA 2 nd SKADS Workshop October 2007 Large gate periphery InGaAs/InAlAs pHEMT: Measurement and Modelling for LNA fabrication B. Boudjelida,

Radio Frequency Engineering Lecture #1 Passives - Extra Stepan Lucyszyn ステファン・ルシズィンインペリアル・カレッジ・ロンドン准教授 Lecture #1 Passives – Extra.

Impedance Matching (2). Outline Three Element Matching – Motivation – Pi Network – T Network Low Q or Wideband Matching Network Impedance Matching on.

Circuit Extraction 1 Outline –What is Circuit Extraction? –Why Circuit Extraction? –Circuit Extraction Algorithms Goal –Understand Extraction problem –Understand.

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors.

EKT 441 MICROWAVE COMMUNICATIONS

Characterization of Circuit Components Using S-Parameters Chapter 1.

On-chip inductance and coupling Zeynep Dilli, Neil Goldsman Thanks to Todd Firestone and John Rodgers for providing the laboratory equipment and expertise.

On-chip Inductors: Design and Modeling UMD Semiconductor Simulation Lab March 2005.

Switching Power Supply Component Selection

1/42 Changkun Park Title Dual mode RF CMOS Power Amplifier with transformer for polar transmitters March. 26, 2007 Changkun Park Wave Embedded Integrated.

Adapted from Digital Integrated Circuits, 2nd Ed. 1 IC Layout.

Design of RF CMOS Low Noise Amplifiers Using a Current Based MOSFET Model Virgínia Helena Varotto Baroncini Oscar da Costa Gouveia Filho.

ECE201 Lect-171 Capacitors (6.1); Inductors (6.2); LC Combinations (6.3) Dr. Holbert April 5, 2006.

Presented by Paul Kasemir and Eric Wilson

EM-sensitive components on semiconductor chips Modern RF circuits often feature on-chip inductors required by circuit design –Operating frequencies are.

CMOS Technology Characterization for Analog and RF Design Author : Behzad Razavi Presenter : Kyungjin Yoo.

Microwave Interference Effects on Device,

An Integrated Solution for Suppressing WLAN Signals in UWB Receivers LI BO.

Circuit characterization and Performance Estimation

Circuit Characterization Feb 4, Basic Device Equations (p.51)  Cutoff region: V gs  V t  I ds = 0  Linear/non-saturation region: 0

Lecture 101 Capacitors (5.1); Inductors (5.2); LC Combinations (5.3) Prof. Phillips March 7, 2003.

Chapter 6 FM Circuits.

RF Wakeup Sensor – On-Demand Wakeup for Zero Idle Listening and Zero Sleep Delay.

Shunt-Peaking (1) By connecting an inductor in series with the load resistor (series connection in shunt with output), more current is used, for a longer.

RF MEMS devices Prof. Dr. Wajiha Shah. OUTLINE  Use of RF MEMS devices in wireless and satellite communication system. 1. MEMS variable capacitor (tuning.

A 5 GHz Voltage Controlled Oscillator (VCO) with 360° variable phase outputs Presented by Tjaart Opperman (  Program: (MEng) Micro-Electronic.

Varactor Loaded Transmission Lines for Linear Applications Amit S. Nagra ECE Dept. University of California Santa Barbara.

A Dynamic GHz-Band Switching Technique for RF CMOS VCO

Wireless RF Receiver Front-end System – Wei-Liang Chen Wei-Liang Chen Wireless RF Receiver Front-end System Yuan-Ze University, VLSI Systems Lab

PilJae Park 2/23/2007 Slide 1 Transmit/Receive (T/R) Switch Topology Comparison Series-series Topology Series-shunt Topology High impedance block  In.

Chihou Lee, Terry Yao, Alain Mangan, Kenneth Yau, Miles Copeland*, Sorin Voinigescu University of Toronto - Edward S. Rogers, Sr. Dept. of Electrical &

1 Low Phase Noise Oscillators for MEMS inductors Sofia Vatti Christos Papavassiliou.

Microwave Amplifier Design Blog by Ben (Uram) Han and Nemuel Magno Group 14 ENEL 434 – Electronics 2 Assignment

An Ultra-Wideband CMOS VCO with 3~5GHz Tuning Range 指導教授 : 林志明教授學生 : 劉彥均 RFIT IEEE International Workshop on Radio-Frequency Integration Technology,

P ERFORMANCE E NHANCEMENT F OR S PIRAL I NDCUTORS, D ESIGN A ND M ODELING E FE Ö ZTÜRK.

Alternating Current Circuits

Passive components and circuits

Microwave Amplifier Design Blog by Ben (Uram) Han and Nemuel Magno Group 14 ENEL 434 – Electronics 2 Assignment

Design of LNA at 2.4 GHz Using 0.25 µm Technology

Study of 60GHz Wireless Network & Circuit Ahn Yong-joon.

1.  Why Digital RF?  Digital processors are typically implemented in the latest CMOS process → Take advantages scaling. (e.g. density,performance) 

Transformer Based Oscillators

Microwave Traveling Wave Amplifiers and Distributed Oscillators ICs in Industry Standard Silicon CMOS Kalyan Bhattacharyya Supervisors: Drs. J. Mukherjee.

Discontinuities of Microstrip Line

Introduction to SYSTEM-ON-PACKAGE(SOP) Miniaturization of the Entire System © 2008 CHAPTER 5.

EE 4345 Chapter 6 Derek Johnson Michael Hasni Rex Reeves Michael Custer.

CMOS Analog Design Using All-Region MOSFET Modeling 1 CMOS Analog Design Using All-region MOSFET Modeling Chapter 3 CMOS technology, components, and layout.

18/10/20151 Calibration of Input-Matching and its Center Frequency for an Inductively Degenerated Low Noise Amplifier Laboratory of Electronics and Information.

Alternating Current Circuits. Resistance Capacitive Reactance, X C.

A High-Gain, Low-Noise, +6dBm PA in 90nm CMOS for 60-GHz Radio

Arun N. Chandorkar Department of Electrical Engineering

A NEW METHOD TO STABILIZE HIGH FREQUENCY HIGH GAIN CMOS LNA RF Communications Systems-on-chip Primavera 2007 Pierpaolo Passarelli.

RFIC – Atlanta June 15-17, 2008 RTU1A-5 A 25 GHz 3.3 dB NF Low Noise Amplifier based upon Slow Wave Transmission Lines and the 0.18 μm CMOS Technology.

1 A Literature Review About Q-enhancement Filter design.

1 © Unitec New Zealand DE4401 AC R L C COMPONENTS.

微波工程期中報告老師：陳文山班級：碩研電子一甲姓名：朱士豪學號： M On-Die Synthesized Inductors: Boon or Bane? Jim Wight, John R. Long,L. Richard Carley,and Tom Riley.

Ph.D. Candidate: Yunlei Li Advisor: Jin Liu 9/10/03

1 Decoupling Capacitors Requirements Intel - Microprocessor power levels in the past have increased exponentially, which has led to increased complexity.

Rakshith Venkatesh 14/27/2009. What is an RF Low Noise Amplifier? The low-noise amplifier (LNA) is a special type of amplifier used in the receiver side.

INTEGRATED CIRCUITS Dr. Esam Yosry Lec. #8. VLSI Components in CMOS Technology  Introduction  Resistor Design  Capacitor Design  Inductor Design 

Chapter 4: Secs ; Chapter 5: pp

LUMPED ELEMENTS ECB 3211 – RF & Microwave Engineering Module - I SOURCE: RF & Microwave Handbook, CRC Press 1.

RF Systems Frequency Converter Principles Adding Sinusoidal Waves Multiplying Sinusoidal Waves Using FET’s for Sinus Multiplication Layout Considerations.

RF Systems Target Radio-Frequencies Wireless communication systems require specific radio- frequency integrated circuits, which often require optimum performances.

WEBENCH® Coil Designer

Chapter 3 Inductance and Capacitance

Presentation transcript:

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Physical creation of passive integrated components Layout and photo-micrograph of 1.5 micron CMOS elements Integrated Inductor Integrated Poly-Poly Capacitor

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Major focus on specific capacitance and inductance values Differs from parasitic capacitance and inductance which abound on-chip Capacitance Inductance Uses of Passive Integrated Elements DC block, AC coupling, AC bypass Filtering, Matching DC biasing Filtering, Matching

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Uses of Passive Integrated Elements: Examples Cascode LNA with Matching MOS VCO (C4 and C5 VVC)

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Capacitors in MOS

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitance generated from conductor overlays Most used overlay: metal-metal and poly- poly Basic structure based on parallel plate capacitance (neglects fringing) Capacitors

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors C a – capacitance per unit area: aF/  m 2 Typical values 1.0 pF capacitor

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Layer Tradeoffs P-P: higher capacitance per unit area, higher sheet resistance M-M; lower capacitance per unit area, lower sheet resistance Impacts Equivalent Circuit Capacitors

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (top/bottom plate) R3, R4, C4, C5: substrate losses Metal-metal Poly-poly

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (C3 > C2) R3, R4, C4, C5: substrate losses

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Capacitors R1, R2: plate/layer losses C1: desired capacitance C2, C3: parasitic capacitance (C2 > C3) R3, R4, C4, C5: substrate losses

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Design and determine the equivalent circuit (neglecting substrate effects) of a 2.8pF poly-poly capacitor with 50 micron overlap on each side. Capacitors: An Example

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Capacitors in MOS: Simulation and Experimental Results

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Example: Metal2-Metal1 floating capacitor Capacitors Technology: 1.5 micron CMOS Area: 105 by 64 microns RF wafer probing Frequency Range: GHz

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Layer Metal 1 Layer

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Poly-poly floating capacitor Capacitors Technology: 1.5 micron CMOS Area: 78 by 64 microns RF wafer probing Contacts de-embedded Frequency Range: GHz Series Capacitor Target: 2.8 pF

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Poly2 Poly 1 S 21 S 11

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified capacitor model Measured S-parameter data Target Design Measured Equivalent Circuit C1: 2.8 pFC1: 2.84 pF, R1, R2=26, 24 Ohms Resulting C2: 0.18pF/0.18pF C2/C3: 0.02pF/ 0.387pF Experimental Results

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors in MOS

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors Figure of Merit for Inductor Integrated inductors suffer from low Q (4-10) L doesn’t scale like FET Traditional RF circuits have several inductors Self-resonance: Q=0

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Equations d out d in Parasitic capacitance and resistance important for element Q and resonant frequency Moran

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Equations d out d in Parasitic Capacitance Parasitic Resistance Length, width, spacing contribute to overall inductor frequency response.

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Equivalent Circuit Model L: desired inductance R1: conductive layer loss C1, C2: parasitic layer capacitance R2, R3, C3, C4: substrate losses Use top-most metal layer for the majority of the inductor for reduced parasitics

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductor: Design Example 150  m 250  m N= micron CMOS Inductor

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Integrated Inductors: Design Example 150  m 250  m N=7.5

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Numerical Simulation Results Metal 2 Layer Metal 1 Layer

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Measured Results: Comparison

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. 2-level metal inductor with plain substrate Inductor Measurements Technology: 1.5 micron CMOS Area: 78 by 64 microns RF wafer probing Contacts de-embedded Frequency Range: GHz

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified inductor model S-parameter data Design ParametersMeasured Parameters Inductor Measurements

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Simplified inductor model Design ParametersComputed Parameters Inductor Measurements 900 MHz Results R = 26 Ohms L = 6.1 nH

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Advanced Modeling Substrate Effects Two substrate effects Substrate losses (Rsub, Csub) Substrate Coupling (Rcoup, Ccoup)

Passive Integrated Elements Robert H. Caverly, Villanova University The creation of these notes was supported by a Grant from The National Science Foundation. Bibliography “A simple wideband on-chip inductor model for silicon-based RF ICs”, J. Gil and H. Shin, IEEE MTT-51(9), p 2023, S. S. Mohan, et al., “Simple Accurate Expressions for Planar Spiral Inductances”, IEEE Journal of Solid-State Circuits, October 1999, pp B. Razavi, RF Microelectronics, Prentice Hall, Upper Saddle River, NJ, Y. Chu, H. Chuang, “A fully integrated 5.8 GHz U-NII band 0.18  m CMOS VCO”, IEEE Micro. Wireless Components Lett., vol. 13(7), p. 287, 2003.