ELEC Digital Logic Circuits Fall 2014 Delay and Power Vishwani D. Agrawal James J. Danaher Professor Department of Electrical and Computer Engineering Auburn University, Auburn, AL Fall 2014, Nov 21 ELEC Lecture 8 1

Delay: Definitions Rise time is the time a signal takes to rise from 10% to 90% of its peak value. Fall time is the time a signal takes to drop from 90% to 10% of its peak value. Delay of a gate is the time interval between the input crossing 50% of peak value and the output crossing 50% of peak value. Fall 2014, Nov 21 ELEC Lecture 8 2 1→1 1→0 0→1 NAND gate A B C VDD GND Fall timeB Time 10% VDD 90% VDD VDD GND Rise timeC Time 10% VDD 90% VDD Gate delay

Fall 2014, Nov 21 ELEC Lecture 8 3 Consider Delay of Inverter (Other Gates are Similar) In Out → to fanout gates C1C1 C2C2 V DD GND C W + C G-in Source Drain Source 1→0 0→1

Fall 2014, Nov 21 ELEC Lecture 8 4 Capacitances in MOSFET SourceDrain Gate oxide Gate Bulk CsCs CdCd CgCg C gd C gs R. C. Jaeger and T. N. Blalock, Microelectronic Circuit Design, Boston: McGraw-Hill, W L L = Channel length (fixed) W = Width (transistor size) t ox = Oxide thickness

Fall 2014, Nov 21 ELEC Lecture 8 5 Gate Capacitance C g = ε ox WL / t ox = C permicron W ε ox C permicron =── L t ox where ε ox = 3.9ε 0 for Silicon dioxide = 3.9 × 8.85 × F/cm

Fall 2014, Nov 21 ELEC Lecture 8 6 Propagation Delay of a Transition V DD Ground CLCL R on R = large v i (t) v o (t) i c (t) C L =Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis.

Fall 2014, Nov 21 ELEC Lecture 8 7 Charging of a Capacitor V DD C = C L R = R on i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

Fall 2014, Nov 21 ELEC Lecture 8 8 i(t)=C dv(t)/dt=[V DD – v(t)] /R dv(t) dt ∫ ───── = ∫ ──── V DD – v(t) RC – t ln [V DD – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V DD – t v(t) =V DD [1 – exp(───)] = 0.5V DD RC t = 0.69 RC

Fall 2014, Nov 21 ELEC Lecture 8 9 Inverter: Idealized Input t = 0 V DD 0.5V DD GND V DD GND time 0.69CR INPUT OUTPUT Gate delay

Large Circuit Timing Analysis Determine gate delays: From layout analysis, or use approximate delays: –Gate delay increases in proportion to number of fanouts (increased capacitance) –Delay decreases in proportion to gate size increase (reduced transistor channel resistance) Purpose of analysis is to verify timing behavior – determine maximum speed of operation. Methods of analysis: Circuit simulation – most accurate, expensive (Spice program) Event-driven logic simulation – efficient, accurate Static timing analysis (STA) – most efficient, approximate Fall 2014, Nov 21 ELEC Lecture 8 10

Fall 2014, Nov 21 ELEC Lecture 8 11 Static Timing Analysis (STA) Combinational logic for critical path delays. Circuit represented as an acyclic directed graph (DAG). Gates characterized by delays. No inputs are used – worst-case analysis – static analysis (simulation is dynamic).

Fall 2014, Nov 21 ELEC Lecture 8 12 Example A1A1 B3B3 D2D2 E1E1 F1F1 J1J1 G 2 H3H Levelize graph. Initialize arrival times at primary inputs to 0. Level C1C1 Gate delay Level of a gate is one greater than the maximum of fanin gate levels

Fall 2014, Nov 21 ELEC Lecture 8 13 Example (Cont.) A1A1 B3B3 C1C1 D2D2 E1E1 F1F1 J1J1 G2G2 H3H Determine output arrival time when all input arrival times are known Level Largest of input delays + gate delay

Fall 2014, Nov 21 ELEC Lecture 8 14 Example (Cont.) A1A1 B3B3 C1C1 D2D2 E1E1 F1F1 J1J1 G2G2 H3H Trace critical path from the output with longest arrival time Level Critical path Delay = 10

Fall 2014, Nov 21 ELEC Lecture 8 15 Path Analysis Algorithms for Directed Acyclic Graphs (DAG) Graph size: n = |V| + |E|, for |V| vertices and |E| edges. Levelization: O(n) (linear-time) algorithm finds the maximum (or minimum) depth. Path counting: O(n 2 ) algorithm. Number of paths can be exponential in n. Finding all paths: Exponential-time algorithm. Shortest (or longest) path between two nodes: – –Dijkstra’s algorithm: O(n 2 ) – –Bellman-Ford algorithm: O(n 3 )

Fall 2014, Nov 21 ELEC Lecture 8 16 References Delay modeling, simulation and testing: – –M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits, Springer, Analysis and Design: – –G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, – –N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, PrimeTime (Static timing analysis tool): – –H. Bhatnagar, Advanced ASIC Chip Synthesis, Second Edition, Springer, 2002

Fall 2014, Nov 21 ELEC Lecture 8 17 CMOS Logic (Inverter) F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid- State Circuits Conference Digest, vol. IV, February 1963, pp No current flows from power supply! Where is power consumed? VDD GND

Fall 2014, Nov 21 ELEC Lecture 8 18 Components of Power Dynamic, when output changes –Signal transitions (major component) Logic activity Glitches –Short-circuit (small) Static, when signal is in steady state –Leakage (used to be small) P total =P dyn + P stat =P tran + P sc + P stat

Charging of Output Capacitor From Slide 8: Fall 2014, Nov 21 ELEC Lecture 8 19 – t v(t)=V [1 – exp( ── )] RC dv(t) V – t i(t)=C ───=── exp( ── ) dt R RC

Fall 2014, Nov 21 ELEC Lecture 8 20 Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

Fall 2014, Nov 21 ELEC Lecture 8 21 Energy Dissipated Per Transition in Transistor Channel Resistance ∞ V 2 ∞ -2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

Fall 2014, Nov 21 ELEC Lecture 8 22 Energy Stored in Charged Capacitor ∞∞ - t V - t ∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt 00 RC R RC 1 = ─ CV 2 2

Fall 2014, Nov 21 ELEC Lecture 8 23 Transition Power Gate output rising transition – –Energy dissipated in pMOS transistor = CV 2 /2 – –Energy stored in capacitor = CV 2 /2 Gate output falling transition – –Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor f ck = clock frequency

Fall 2014, Nov 21 ELEC Lecture 8 24 Components of Power Dynamic –Signal transitions Logic activity Glitches –Short-circuit Static –Leakage P total =P dyn + P stat =P tran + P sc + P stat Delay =1 0 0 Delay= GLITCH

Fall 2014, Nov 21 ELEC Lecture 8 25 Short Circuit Power of a Transition: P sc V DD Ground CLCL v i (t) v o (t) i sc (t)

Fall 2014, Nov 21 ELEC Lecture 8 26 Short-Circuit Power Increases with rise and fall times of input. Decreases for larger output load capacitance; large capacitor takes most of the current. Small, about 5-10% of dynamic power; momentary shorting of supply and ground during opening and closing of transistor switches.

Fall 2014, Nov 21 ELEC Lecture 8 27 Components of Power Dynamic – –Signal transitions Logic activity Glitches – –Short-circuit Static – –Leakage

Fall 2014, Nov 21 ELEC Lecture 8 28 Static (Leakage) Power Reason: Resistance of an open transistor switch is large but not infinite. Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Static power increases as feature size is scaled down; controlling leakage is an important aspect of transistor design and semiconductor process technology.

Fall 2014, Nov 21 ELEC Lecture 8 29 CMOS Gate Power V Ground C R = R on Large resistance v i (t) v(t) i(t) time v(t) i(t) i sc (t) Leakage current i sc (t) Output signal transition Dynamic current Short-circuit current Leakage current