Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan ELEC / Spring 2015 Low-Power Design of Electronic Circuits Power Dissipation of CMOS Circuits Vishwani D. Agrawal James J. Danaher Professor Dept. of Electrical and Computer Engineering Auburn University, Auburn, AL

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan nMOS Logic (Inverters) Saturated-load nMOS Pseudo-nMOS For logic 1 input, continuous static power is dissipated. R. C. Jaeger and T. N. Blalock, Microelctronic Circuit Design, Third Edition, McGraw-Hill, 2006, Chapter 6.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan CMOS Logic (Inverter) F. M. Wanlass and C. T. Sah, “Nanowatt Logic using Field-Effect Metal-Oxide-Semiconductor Triodes,” IEEE International Solid- State Circuits Conference Digest, vol. IV, February 1963, pp No current flows from power supply! Where is power consumed? VDD GND

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit (small) Short-circuit (small) Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Power of a Transition: P tran V = V DD Ground C = C L R = R on Large resistance v i (t) v(t) i(t) C =Total load capacitance for gate; includes transistor capacitances of driving gate + routing capacitance + transistor capacitances of driven gates; obtained by layout analysis.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Charging of a Capacitor V C R i(t) i(t) v(t) Charge on capacitor, q(t)=C v(t) Current, i(t)=dq(t)/dt=C dv(t)/dt t = 0

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan i(t)=C dv(t)/dt=[V – v(t)] /R dv(t)V – v(t) ───=───── dt RC dv(t) dt ∫ ─────= ∫ ──── V – v(t) RC – t ln [V – v(t)]=──+ A RC Initial condition, t = 0, v(t) = 0 → A = ln V – t v(t)=V [1 – exp(───)] RC

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan – t v(t)=V [1 – exp( ── )] RC dv(t) V – t i(t)=C ───=── exp( ── ) dt R RC

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Total Energy Per Charging Transition from Power Supply ∞∞ V 2 – t E trans =∫ V i(t) dt=∫ ── exp( ── ) dt 00 R RC =CV 2

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Energy Dissipated per Transition in Resistance ∞ V 2 ∞ – 2t R ∫ i 2 (t) dt=R ── ∫ exp( ── ) dt 0 R 2 0 RC 1 = ─ CV 2 2

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Energy Stored in Charged Capacitor ∞∞ – t V – t ∫ v(t) i(t) dt = ∫ V [1-exp( ── )] ─ exp( ── ) dt 00 RC R RC 1 = ─ CV 2 2

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Transition Power Gate output rising transition Gate output rising transition Energy dissipated in pMOS transistor = CV 2 /2 Energy dissipated in pMOS transistor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Energy stored in capacitor = CV 2 /2 Gate output falling transition Gate output falling transition Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated in nMOS transistor = CV 2 /2 Energy dissipated per transition = CV 2 /2 Energy dissipated per transition = CV 2 /2 Power dissipation: Power dissipation: P trans =E trans α f ck =α f ck CV 2 /2 α=activity factor f ck =clock frequency

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage P total =P dyn + P stat =P tran + P sc + P stat Delay =1 0 0 Delay= GLITCH

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short Circuit Power of a Transition: P sc V DD Ground CLCL v i (t) v o (t) i sc (t)

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short Circuit Current, i sc (t) Time (ns) 0 1 I sc Volt V DD i sc (t) 0 V i (t) V o (t) V DD - V Tp V Tn tBtB tEtE I scmaxf p-transistor starts conducting n-transistor cuts-off

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Peak Short Circuit Current Increases with the size (or gain, β) of transistors Increases with the size (or gain, β) of transistors Decreases with load capacitance, C L Decreases with load capacitance, C L Largest when C L = 0 Largest when C L = 0 Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp Reference: M. A. Ortega and J. Figueras, “Short Circuit Power Modeling in Submicron CMOS,” PATMOS ’96, Aug. 1996, pp

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short-Circuit Energy per Transition E scf =∫ tB t E V DD i sc (t)dt E scf =∫ tB t E V DD i sc (t)dt = (t E – t B ) I scmaxf V DD / 2 = (t E – t B ) I scmaxf V DD / 2 E scf = t f (V DD - |V Tp | - V Tn ) I scmaxf / 2 E scf = t f (V DD - |V Tp | - V Tn ) I scmaxf / 2 E scr = t r (V DD - |V Tp | - V Tn ) I scmaxr / 2 E scr = t r (V DD - |V Tp | - V Tn ) I scmaxr / 2 E scf = E scr = 0, when V DD = |V Tp | + V Tn E scf = E scr = 0, when V DD = |V Tp | + V Tn

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short-Circuit Power Increases with rise and fall times of input. Increases with rise and fall times of input. Decreases for larger output load capacitance; large capacitor takes most of the current. Decreases for larger output load capacitance; large capacitor takes most of the current. Small, about 5-10% of dynamic power; momentary shorting of supply and ground during opening and closing of transistor switches. Small, about 5-10% of dynamic power; momentary shorting of supply and ground during opening and closing of transistor switches.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short-Circuit Power Calculation Assume equal rise and fall times Assume equal rise and fall times Model input-output capacitive coupling (Miller capacitance) Model input-output capacitive coupling (Miller capacitance) Use a spice model for transistors Use a spice model for transistors T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp T. Sakurai and A. Newton, “Alpha-power Law MOSFET model and Its Application to a CMOS Inverter,” IEEE J. Solid State Circuits, vol. 25, April 1990, pp

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Short Circuit Power P sc =α f ck E sc

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan P sc, Rise Time and Capacitance V DD Ground CLCL R on R = large v i (t) v o (t) i c (t)+i sc (t) tftf trtr v o (t) ─── R↑ v o (t) V DD

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan i sc, Rise Time and Capacitance – t V DD [ 1 – exp ( ───── )] v o (t) R↓(t) C I sc (t) =──── =─────────────── R↑(t)

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan i scmax, Rise Time and Capacitance Small C Large C tftf 1 ──── R↑(t) i scmax v o (t) i t

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan P sc, Rise Times, Capacitance For given input rise and fall times short circuit power decreases as output capacitance increases. For given input rise and fall times short circuit power decreases as output capacitance increases. Short circuit power increases with increase of input rise and fall times. Short circuit power increases with increase of input rise and fall times. Short circuit power is reduced if output rise and fall times are longer than the input rise and fall times. Short circuit power is reduced if output rise and fall times are longer than the input rise and fall times.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Summary: Short-Circuit Power Short-circuit power is consumed by each transition (increases with input transition time). Short-circuit power is consumed by each transition (increases with input transition time). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Reduction requires that gate output transition should not be faster than the input transition (faster gates can consume more short-circuit power). Increasing the output load capacitance reduces short-circuit power. Increasing the output load capacitance reduces short-circuit power. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp | + V tn. Scaling down of supply voltage with respect to threshold voltages reduces short-circuit power; completely eliminated when V DD ≤ |V tp | + V tn.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Components of Power Dynamic Dynamic Signal transitions Signal transitions Logic activity Logic activity Glitches Glitches Short-circuit Short-circuit Static Static Leakage Leakage

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Leakage Power IGIG IDID I sub I PT I GIDL n+ Ground V DD R DrainSource Gate Bulk Si (p) nMOS Transistor

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Leakage Current Components Subthreshold conduction, I sub Subthreshold conduction, I sub Reverse bias pn junction conduction, I D Reverse bias pn junction conduction, I D Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Gate induced drain leakage, I GIDL due to tunneling at the gate-drain overlap Drain source punchthrough, I PT due to short channel and high drain-source voltage Drain source punchthrough, I PT due to short channel and high drain-source voltage Gate tunneling, I G through thin oxide; may become significant with scaling Gate tunneling, I G through thin oxide; may become significant with scaling

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Drain to Source Current I DS = μ 0 C ox (W/L) V t 2 exp{(V GS –V TH ) / nV t } μ 0 : carrier surface mobility C ox : gate oxide capacitance per unit area L: channel length W: gate width V t = kT/q: thermal voltage n: a technology parameter

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan I DS for Short Channel Device I DS = μ 0 C ox (W/L)V t 2 exp{(V GS –V TH + ηV DS )/nV t } V DS = drain to source voltage η: a proportionality factor W. Nebel and J. Mermet (Editors), Low Power Design in Deep Submicron Electronics, Springer, 1997, Section 4.1 by J. Figueras, pp

Subthreshold Current, I sub Example: 90nm CMOS inverter Example: 90nm CMOS inverter L = 90nm, W p = 495nm, W n = 216nm L = 90nm, W p = 495nm, W n = 216nm Temperature 300K (room temperature) Temperature 300K (room temperature) Input set to 0 volt Input set to 0 volt V thn = 0.291V, V thp = 0.209V at V DD = 1.2V (nominal) V thn = 0.291V, V thp = 0.209V at V DD = 1.2V (nominal) PTM (predictive technology model) PTM (predictive technology model) Spice simulation for leakage current Spice simulation for leakage current Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan

Subthreshold Current, I sub Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan

Subthreshold Current, I sub Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Increased Subthreshold Leakage 0V TH ’V TH Log (Drain current) Gate voltage Scaled device IcIc I sub

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Summary: Leakage Power Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. Leakage power as a fraction of the total power increases as clock frequency drops. Turning supply off in unused parts can save power. For a gate it is a small fraction of the total power; it can be significant for very large circuits. For a gate it is a small fraction of the total power; it can be significant for very large circuits. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Scaling down features requires lowering the threshold voltage, which increases leakage power; roughly doubles with each shrinking. Multiple-threshold devices are used to reduce leakage power. Multiple-threshold devices are used to reduce leakage power.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan CMOS Gate Power V Ground C R = R on Large resistance v i (t) v(t) i(t) time v(t) i(t) i sc (t) Leakage current i sc (t)

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Technology Scaling Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies Scaling down 0.7 micron by factors 2 and 4 leads to 0.35 and 0.17 micron technologies Constant electric field assumed Constant electric field assumed

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Constant Electric Field Scaling B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp B. Davari, R. H. Dennard and G. G. Shahidi, “CMOS Scaling for High Performance and Low Power—The Next Ten Years,” Proc. IEEE, April 1995, pp Other forms of scaling are referred to as constant-voltage and quasi-constant- voltage. Other forms of scaling are referred to as constant-voltage and quasi-constant- voltage.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Bulk nMOSFET n+ p-type body (bulk) n+ L W SiO 2 Thickness = t ox Gate Source Drain Polysilicon

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Technology Scaling A scaling factor (S ) reduces device dimensions as 1/S. A scaling factor (S ) reduces device dimensions as 1/S. Successive generations of technology have used a scaling, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm, 32nm and 22nm. Successive generations of technology have used a scaling S = √2, doubling the number of transistors per unit area. This produced 0.25μ, 0.18μ, 0.13μ, 90nm and 65nm technologies, continuing on to 45nm, 32nm and 22nm. A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. A 5% gate shrink (S = 1.05) is commonly applied to boost speed as the process matures. N. H. E. Weste and D. Harris, CMOS VLSI Design, Third Edition, Boston: Pearson Addison-Wesley, 2005, Section

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Constant Electric Field Scaling Device Parameter Scaling Length, L 1/S Width, W 1/S Gate oxide thickness, t ox 1/S Supply voltage, V DD 1/S Threshold voltages, V tn, V tp 1/S Substrate doping, N A S

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Constant Electric Field Scaling(Cont.) Device Characteristic Scaling β W / (L t ox ) S Current, I ds β (V DD – V t ) 2 β (V DD – V t ) 2 1/S Resistance, R V DD / I ds 1 Gate capacitance, C W L / t ox 1/S Gate delay, τ RC 1/S Clock frequency, f 1/ τ S Dynamic power per gate, P CV 2 f 1/S 2 Chip area, A 1/S 2 Power density P/A1 Current density I ds /A S

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Problem: A Design Example A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power. The short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. A battery-operated 65nm digital CMOS device is found to consume equal amounts (P ) of dynamic power and leakage power. The short-circuit power is negligible. The energy consumed by a computing task, that takes T seconds, is 2PT. Compare two power reduction strategies for extending the battery life: Compare two power reduction strategies for extending the battery life: A. A.Clock frequency is reduced to half, keeping all other parameters constant. B. B.Supply voltage is reduced to half. This slows the gates down and forces the clock frequency to be lowered to half of its original (full voltage) value. Assume that leakage current is reduced by a ratio 10/2 = 5 (see slides 32 and 33).

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Solution: Strategy A. Clock Frequency Reduction Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Reducing the clock frequency will reduce dynamic power to P / 2, keep the static power the same as P, and double the execution time of the task. Energy consumption for the task will be, Energy consumption for the task will be, Energy = (P / 2 + P ) 2T = 3PT which is greater than the original 2PT.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Solution: Part B. Supply Voltage Reduction When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 10. The time of task is doubled and the total energy consumption is, When the supply voltage and clock frequency are reduced to half their values, dynamic power is reduced to P / 8 and static power to P / 10. The time of task is doubled and the total energy consumption is, Energy = (P / 8 + P / 10) 2T = 9PT / 20 =0.45PT The voltage reduction strategy reduces energy consumption while a simple frequency reduction consumes more energy.

Copyright Agrawal 2007ELEC / Spr 2015 Lecture 2 Jan Comparing Strategies A and B OriginalAB VoltageVVV/2 Clock FrequencyFF/2 Task DurationT2T Power2P1.5P0.225P Energy2PT3PT0.45PT