RD53 1

 Full/large demonstrator chip submission ◦ When: 2016 A.Early 2016: If chip must have been fully demonstrated in test beams for TDRs to be made in  Will be high risk submission  Uncertain if we can get project team together for this B.Mid-End 2016: Assuring that all building blocks have been well tested, radiation qualified and global design thoroughly verified. ◦ Cost: ~1M $/Euro/CHF (we better get this right) A.1M: Full engineering run for full scale chip B.700k: Reduced size chip using MLM C.Shared engineering run with others (~300k from others).  RD53 will take majority (2/3) of reticle to make 2x2cm 2 chip  Schedule driven by RD53  Converge distributed WG work to single chip design  Converge on specifications, architecture, etc.  All RD53 activities must converge on this “final” goal 2

 “Full” size chip: ~2 x 2cm  Small pixels: 50x50, 25x100um 2 ◦ Appropriate also for large pixels: 50 x 100um 2, 100x100um 2, 50 x 200um 2  Very high rate capability: 3GHz  Effective threshold (25ns in time): ~1000e ◦ Very low cross-talk from digital ◦ Threshold adjust, noise, etc.  Radiation tolerance: 1Grad (500Mrad)  SEU tolerance  Long trigger latency: 10us (20)  High trigger rate: ~1MHz  Low power: < 1W/cm 2 (as low as possible)  Appropriate powering scheme for chip and system  Test with bump bonded pixel sensors: Planar & 3D  Specific features for pixel sensor R&D program : ◦ Extended charge resolution: 8-10 bit (low hit rates) ◦ Bump bonding pattern and bump bonding pad to enable BB to R&D pixel sensors. ◦ Other ?  Les critical, but we still would like this in DEMO: ◦ Test and Calibration features ◦ Monitoring ◦ On-chip data compression ◦ High speed readout interface with optimized electrical link drivers 3

 Radiation characterization of 65nm ◦ Define appropriate radiation qualification protocol ◦ TID test of basic transistors: X-ray, cobalt, 3Mev protons  Room temp  Cold: -20  Annealing ◦ NIEL radiation test ◦ Compare with similar technologies ◦ Test of basic circuits (analog/digital)  Realist radiation hardness goal: 1Grad or 500Mrad ◦ 500Mrad implies exchange of inner layer after 5 years.  Rad hard design recommendation: ◦ Analog: Guidelines for transistor sizes, etc. ◦ Digital: Minimum size transistors, speed degradation, (appropriate digital library)  Radiation simulation corner: Analog and digital Work in IP/FE /TOP WGs depend critically on this ! 4

 Define basic specs of FE.  Define appropriate FEs to be designed/tested  Design of FEs  Prototype(s)  Electrical test  Radiation tests  Define common FE interface to digital part  Finalize FE’s for integration in digital  2 nd. iteration  (Final prototype) 5

 Define list of IPs ( 20)  Initial specs of IPs  Design of IPs  Prototyping of IPs  Electrical tests  Customized digital library ?  Radiation test  Integration into global design ◦ Common repository with  IO, Simulation models, etc.  2 nd. iteration  (Final prototype) 6

 Define control/timing protocol  Define readout protocol  Readout port cable driver  IO implementation in RTL  (Prepare pixel chip readout system) 7

 Simulation frame work  Simulation of existing pixel chip (FEI4)  Import of MC data and mix with internal data  Architectural studies  SEU injection and verification  Verification plan  Verification of full pixel chip 8

 Define global specifications  Define global floorplan: ◦ Digital sea with analog islands ◦ Sensor interface: BB interface ◦ Power and biasing distribution  Small scale prototype to check global floorplan and tool chain  Define global powering scheme and power distribution  Define, design and verify final architecture ◦ Power optimization ◦ Fit in available area ◦ SEU verification 9

 Radiation test of technology: ◦ Design recommendations for analog & digital ◦ Radiation qualification protocol ◦ Radiation simulation corner  Design of FE/IPs/(digital library)  FE/IP Prototyping and electrical tests  FE/IP Radiation test  FE/IP Modifications  (2 nd IP/FE prototype with radiation test)  Integration in full Demo pixel chip  Demo pixel chip verification 10

 Q3 2015: ◦ Pixel array architecture optimization (pixel, pixel region, pixel core)  Sim WG: Simulation framework with hit/trigger input data and reference model  Q4 2015: ◦ Global architecture optimization (EOC, config, etc.) ◦ Integration/verification of IO interfaces  IO WG: IO interface defined and implemented in sim. framework ◦ Integration of FE & IPs  IP, FE WGs: Initial version of IP/FE simulation models  Q1 2016: ◦ RTL description of full chip and basic verification with SEU  Sim WG: Simulation framework with SEU injection/verification ◦ Synthesis and P&R of critical blocks (pixel region logic)  IP WG: Final digital library ◦ Basic Power and RTL optimization  Q2 2016: ◦ Verification with final IPs  IP/FE WG: Final FEs/IPs ◦ Detailed RTL/power/size optimization  Q3 2016: ◦ Detailed functional verification: ◦ Sim WG: Support for all modes and detailed options of pixel chip.  Q : ◦ Final design assembly and verification: P&R, timing, power, cross-talk, DRC, chip ring, etc. ◦ Submission Global DEMO design team Q – Q4 2016: 12 – 16 months 11

 Q : Submission  Q1 2017: Electrical/radiation tests ◦ Test setup and software must be made beforehand  Q2 2017: Bump-bonding to sensor ◦ Sensors and contract for BB must be in place  Q3-Q4 2017: Test beams 12

 Rad:1Grad or 500Mrad ?. NIEL radiation tests Analog design recommendations Recommendations for digital library Radiation simulation corner Radiation test procedure for circuits  Analog:Finalize FEs with characterization and rad tests Select appropriate FE(s) Finalize FE(s) for integration in full demonstrator  Sim:Simulate ATLAS/CMS conditions Evaluate architectures and optimize these SEU injection and fault tolerance verification Define appropriate Verification scheme/plan Support for different modes and detailed options.  IO:Define and agree on IO interfaces. Include in simulation model Implement and verify IO in RTL Prepare and implement appropriate test systems  IP:Final specs and interfaces of IPs Finalize IPs with characterization and rad tests Finalize IPs for integration in full demonstrator  TOP:Evaluate different architectures and choose one. Converge to final pixel chip RTL 13

14

 RD53 Institutes:20  RD53 member list: ~140  Active contribution: ~70  Expected FTE 2015:~22 ◦ IP:7.2 ◦ Sim:3.1 ◦ Rad:3.0 ◦ Top:3.0 ◦ IO:1.0 ◦ Org:2.0  >50% involvement: ~15 ◦ Significant fraction are young students  Dispersed/distributed collaboration 15

 Full scale pixel chip in mid-end 2016 ◦ Investigates engineering run sharing with others (e.g. CMS MPA)  Converge work in WGs and get design/project team together  Determine specific features for sensor RD: ◦ Charge resolution, dynamic range, ? ◦ BB pattern and pad.  Non staggered - Staggered  Enable BB of single chips to single sensors 16