12 June 2016 Slide s 2.org Vmin Estimate Model 50K-point IS o/□/Δ MC <5% Vmin error relative to MC (<4.7 σ ) Excellent agreement with IS beyond 5 σ Speed up of ~10 5 x over MC Speed up of ~1.7x over IS Application 1 : for a yield or cell failure probability (P), estimate Vmin

12 June 2016 Slide s 2.org Yield / Cell Failure Probability Estimate Model ______ IS o/□/Δ MC A B C D Vmin RangeP wf / P rf / P hf Assist Strategy AP wf <<P rf read assist only BP wf <1e-4; P rf <1e-4moderate read and write assist CP wf >1e-4; P rf >1e-4aggressive read and write assist DP hf becomes significantneed assistance for hold too Application 2 : at a VDD point, estimate the cell failure probability

12 June 2016 Slide s 2.org  Generic for hold, read and write  Easy to use  Run 1000 Monte Carlo simulation for SNM 0 at each VDD point (e.g. 0.5, 0.6, …, 1.0V)  Extract statistical sensitivity of SNM 0 to VDD  Use the theoretical model to estimate Vmin for a given SRAM yield or cell failure probability  OR estimate the cell failure probability or SRAM yield at a given VDD  Accurate: <5.0% error relative to MC, excellent agreement with IS  Fast: ≥10 5  speed-up for larger SRAMs over MC  Verified with both 90nm and 45nm node Statistical Method Summary

12 June 2016 Slide s 2.org SOI 0.18u Test Chip for Sub-V T SRAM Assess various cell structures (6T, 8T, 10T, sym, asym) Assess various assist methods for read/write/hold In fab now

12 June 2016 Slide s 2.org Exploration of Low Voltage eDRAM Negative WL can exponentially increase Tref (VQ is discharged from 0.4V to 0.3V) Node can be charged to 0.4V with a boosted WLVDD (>0.6V) within 100nS 1Kb eDRAM on SOI 0.18u test chip (C Q =9.52fF) Logic-based eDRAM shows potential advantages in strong inversion [1,2] Can eDRAM compete with SRAM at lower voltage ? Benefits: area, leakage Difficulties: refresh time, write time, smaller signal to sense [1] J. Barth et al. ISSCC 2007 [2] D. Somasekhar et al. ISSCC 2008