R. Kluit Electronics Department Nikhef, Amsterdam. Integrated Circuit Design

Outline ASIC’s ? Why do it ourselves ? So far.. Present Technology and outlook Connectivity IC engineering, (€’s &) tools & people … 19/12/2008IC R. Kluit2

Why use ASIC’s ??? Special conditions: our case: Radiation hardness & detector integration Compared to Commercial off the Shelf (COTS): Small area (integration density) Low mass Low power large quantities (~>10k) 19/12/2008IC R. Kluit3

19/12/2008IC R. Kluit4

IC technologies 19/12/2008IC R. Kluit 5 SiGe, GaAs, BiCMOS, CMOS, SOI, etc HEP => Radiation & availability & costs CMOS 3µm  45nm now in Industry Circuits  Systems on Chip (SOC) 1 st : 1.6 x 11mm, one transistor + R & C : ~150mm 2, 1900M tr, 45nm, 130W 50 years

19/12/2008IC R. Kluit6 ASIC application’s 2 IC’s: 0.25µ CMOS 3 prototypes 9/2000 => prod 3/ PCB’s, IC’s (prod. $43k) Chip-on-board; cleaning & Nikhef ++ Radiation & Area 2004 V. Gromov, P. Timmer, J-D Schipper, R. Kluit

Prototype Pixel chip for gas detectors (GOSSIP), 130nm CMOS, 8ML 16x16 pixel array with preamp, TDC and readout. Design & test 2 man-y. $50k 40 IC’s ++ Sensor integration, Radiation, Power, Mass /12/2008IC R. Kluit7 Front-end IC with read-out electronics e - h + crossing particle Sensor inputs ASIC V. Gromov, R. Kluit

/12/2008IC R. Kluit8 Km3Net: Photo Multiplier front-end: 2ns pulse time & amplitude measurements 0.35um CMOS (AMS) Quantity in exp. ~ 400k, Costs ~€.50/chip Proto design: ¾ m-y. ++ Area, Power, Costs J. Hug, V. Gromov, B. v. d. Heiden

19/12/2008IC R. Kluit9 Design in Collaborations: Si-strip detector front-end (0.25µm) Analog readout & Comparator Contribution to new ATLAS Pixel FE chip Design Internal: IC’s for ALICE (0.25µm) Bandgap reference (130nm) GOSSIP frontend prototype’s (130nm) Km3Net PMT front-end (0.35µm) Most recent Designs

CMOS IC technology Design issues: RregVt, 0Vt, HighVt, LowVt transistors Radiation tolerance (design) Technology Design rules Process variations & matching ESD Rules for Manufacturability 19/12/2008IC R. Kluit10 Bulk CMOS

Present Technologies 19/12/2008IC R. Kluit11 Bulk CMOSSOI Strained silicon Vdd VVdd VVdd 1-1.2VVdd 1VVdd 0.9-1V 6 Al6 Cu7 Cu8 Cu9 Cu feature size: Mass prod. start: Power & gate density scale relative to feature size scaling (x0.7). Vsupply Nr. metal layers radiation tolerant ! ????

“Features” of new Techn. Random Dopant Fluctuations ~100 atoms channel length, 1000 dopants in channel Variations in strain & Gate oxide thickness (~ 5 Line Edge effects: R  of connectivity Solutions in Foundry & Design techniques; Global process variations of 45nm improved w.r.t. 90nm & 65nm ! 19/12/2008IC R. Kluit12

CONNECTIVITY 19/12/2008IC R. Kluit13

Interconnect (gap) 19/12/2008IC R. Kluit14

3D interconnect.. 19/12/2008IC R. Kluit15 Source: Fraunhofer IZM 3D interconnect ! Source: IMEC

3D stacking Advantages: More integration. Integration using mixed technologies for analog & digital functions Costs; 3D with “standard” technologies less €’s then 2D “state of the art”. Fast & low power interconnects. 19/12/2008IC R. Kluit16 strong R&D at Fermilab: R. Yarema, G. Deptuchet al. readout chip with time stamping and sparsification 3 tiers (no sensor yet), attempts with several foundries: Tezzaron, Chartered, IZM, RTI, Ziptronix, MITLL

3D in HEP 19/12/2008IC R. Kluit : IMEC demonstrates fully functional 3D Cu stacked IC’s use Thru Silicon Via’s (TSV) Many options: Technologies; Via 1 st /last W2W, D2W, D2D etc. -Proposed for ATLAS upgrades -In development for ReLaXD -Proposed for ATLAS upgrades -In development for ReLaXD

ENGINEERING 19/12/2008IC R. Kluit18

Euro Practice Cadence platform: Cadence:design entry & layout + analog & digital simulation. Assura: Simulation & Verification Mentor: Calibre for DRC & extraction (Ver.) Synopsys: Logic Simulation, Digital Synthesis, Clock tree generation, Place & Route. Software via Educational programs; affordable (€) BUT maintenance ¼ fte. 19/12/2008IC R. Kluit19 Design Tools

ASIC costs (1) Time: Specification & feasibility studies Design of sub-circuits 1 st prototype(s) (MPW); production & test Re-design, + full function/size design Engineering run & test (2 wafers) Production & test Minimum turn-around: ~2 year (>2m-y) 19/12/2008IC R. Kluit20

Money: Software:2-7k€/y Libraries:0-10k€ Prototyping: 3-50k€ Production: µ:40-90k€, 130nm: 300k€, 90nm: 550k€ for, 65nm >1M€. <10k€, wafer test (300mm) Dicing: ~5k€, packaging … ASIC costs (2) 19/12/2008IC R. Kluit21 Special conditions for 90nm CMOS UMC: ~3.5mm2 for 7,000Euro

19/12/2008IC R. Kluit22 ET Design expertise Technologies: Commercial CMOS AMS 0.35µ: Design-Kit + Lib. IBM 0.25µ PDK + Lib. IBM 0.13µ: PDK + Arm/IBM Lib. People & Expertise : (Electronics department) 2+2 Designers have the skills for IC design. Analog front-ends; device level circuit design Digital design; control blocks & architecture Verilog => synthesis => routing.

ASIC design flow Specification Feasibility/system design Prototyping Testing (statistics) Full chip design Verification Pre-production Testing (statistics) Prod, test & implement. 19/12/2008IC R. Kluit23 Radiation qualification! System prototypes ! Radiation qualification!

Summary 19/12/2008IC R. Kluit24 IC design for Detector electronics: Invest in expertise, need IC specialists -critical mass- Strong interaction Engineer <> Physicist =>need “design team” Need (R&) Development Plan & Mile-stones. Continuity & Commitment

19/12/2008IC R. Kluit25 Thanks

Lithography 19/12/2008IC R. Kluit26 Beginning ~ mid 90’s, the industry started printing sub wavelength feature sizes.

Technologies issues.. 19/12/2008IC R. Kluit27

RC delay 19/12/2008IC R. Kluit28 RC delay not decreasing ! Line edge effects, low-k Dielectric not scaling as fast as size scaling

Supply Voltage 19/12/2008IC R. Kluit29

Digital design flow 19/12/2008IC R. Kluit30

19/12/2008IC R. Kluit31 Productivity gap

Present Technologies (2) Transition to SOI, Vdd to ~1V Radiation tolerance: increasing up to 90nm. Beyond ??? 19/12/2008IC R. Kluit32 ~0.7 2 ~ ~0.7 ~0.7 -2