The FPX KCPSM Module 1 Henry Fu The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the FPX Henry Fu Washington University.

Slides:



Advertisements
Similar presentations
Network II.5 simulator ..
Advertisements

Dr. Rabie A. Ramadan Al-Azhar University Lecture 3
NetFPGA Project: 4-Port Layer 2/3 Switch Ankur Singla Gene Juknevicius
1 SECURE-PARTIAL RECONFIGURATION OF FPGAs MSc.Fisnik KRAJA Computer Engineering Department, Faculty Of Information Technology, Polytechnic University of.
t Popularity of the Internet t Provides universal interconnection between individual groups that use different hardware suited for their needs t Based.
Configurable System-on-Chip: Xilinx EDK
Implementation of DSP Algorithm on SoC. Mid-Semester Presentation Student : Einat Tevel Supervisor : Isaschar Walter Accompaning engineer : Emilia Burlak.
Lecture 7 Lecture 7: Hardware/Software Systems on the XUP Board ECE 412: Microcomputer Laboratory.
Winter 2013 Independent Internet Embedded System - Final A Preformed by: Genady Okrain Instructor: Tsachi Martsiano Duration: Two semesters
Benefits of Partial Reconfiguration Reducing the size of the FPGA device required to implement a given function, with consequent reductions in cost and.
Introduction to Interconnection Networks. Introduction to Interconnection network Digital systems(DS) are pervasive in modern society. Digital computers.
Jon Turner (and a cast of thousands) Washington University Design of a High Performance Active Router Active Nets PI Meeting - 12/01.
The FPX KCPSM Module Exercise 1 Henry Fu The Layered Protocol Wrappers Exercise: Network Data Encryption / Decryption Using ROT13 Algorithm Henry Fu Washington.
Department of Computer Science and Engineering Applied Research Laboratory A TCP/IP Based Multi-Device Programming Circuit David V. Schuehler – Harvey.
SYSTEM-ON-CHIP (SoC) AND USE OF VLSI CIRCUIT DESIGN TECHNOLOGY.
The Layered Protocol Wrappers 1 Florian Braun, Henry Fu The Layered Protocol Wrappers: A Solution to Streamline Networking Functions to Process ATM Cells,
High-Level Interconnect Architectures for FPGAs An investigation into network-based interconnect systems for existing and future FPGA architectures Nick.
Applied research laboratory David E. Taylor Users Guide: Fast IP Lookup (FIPL) in the FPX Gigabit Kits Workshop 1/2002.
High-Level Interconnect Architectures for FPGAs Nick Barrow-Williams.
J. Christiansen, CERN - EP/MIC
Gigabit Kits Workshop August Washington WASHINGTON UNIVERSITY IN ST LOUIS IP Processing Wrapper Tutorial Gigabitkits Workshop August 2001
ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview.
CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington.
Introduction to FPGA Created & Presented By Ali Masoudi For Advanced Digital Communication Lab (ADC-Lab) At Isfahan University Of technology (IUT) Department.
8279 KEYBOARD AND DISPLAY INTERFACING
CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 4 : Demonstration of Machine Problem 1 : CAM-based Firewall Washington.
The FPX KCPSM Module Exercise 1 Henry Fu The FPX KCPSM Module Exercise: Network Data Encryption / Decryption Using ROT13 Algorithm Henry Fu Washington.
Extensible Networking Platform Lockwood / Zuver - Applied Research Laboratory -- Extensible Networking Development of a System-On-Chip Extensible.
FPX Network Platform 1 John Lockwood, Assistant Professor Washington University Department of Computer Science Applied Research.
EE3A1 Computer Hardware and Digital Design
4/19/20021 TCPSplitter: A Reconfigurable Hardware Based TCP Flow Monitor David V. Schuehler.
Lecture 13: Reconfigurable Computing Applications October 10, 2013 ECE 636 Reconfigurable Computing Lecture 11 Reconfigurable Computing Applications.
PROJECT - ZYNQ Yakir Peretz Idan Homri Semester - winter 2014 Duration - one semester.
Hot Interconnects TCP-Splitter: A Reconfigurable Hardware Based TCP/IP Flow Monitor David V. Schuehler
Lecture 12: Reconfigurable Systems II October 20, 2004 ECE 697F Reconfigurable Computing Lecture 12 Reconfigurable Systems II: Exploring Programmable Systems.
Field Programmable Port Extender (FPX) 1 Modular Design Techniques for the FPX.
Washington WASHINGTON UNIVERSITY IN ST LOUIS 1 DTI Visit - John DeHart- 4/25/2001 Agenda l WU/ARL Background – John DeHart (15 minutes) l DTI Background.
Field Programmable Port Extender (FPX) 1 NCHARGE: Remote Management of the Field Programmable Port Extender (FPX) Todd Sproull Washington University, Applied.
8279 KEYBOARD AND DISPLAY INTERFACING
CDA 4253 FPGA System Design The PicoBlaze Microcontroller
Field Programmable Port Extender (FPX) 1 Simulation of the Hello World Application for the Field-programmable Port Extender (FPX) Dave Lim and John Lockwood.
Field Programmable Port Extender (FPX) 1 Example RAD Design: IP Router using Fast IP Lookup.
Field Programmable Port Extender (FPX) 1 Software Tools for the Field Programmable Port Extender (FPX) Todd Sproull Washington University, Applied Research.
PARBIT Tool 1 PARBIT Partial Bitfile Configuration Tool Edson L. Horta Washington University, Applied Research Lab August 15, 2001.
CS/CoE 536 : Lockwood 1 CS/CoE 536 Reconfigurable System On Chip Design Lecture 11 : Priority and Per-Flow Queuing in Machine Problem 3 (Revision 2) Washington.
Field Programmable Port Extender (FPX) 1 Modular Design Techniques for the Field Programmable Port Extender John Lockwood and David Taylor Washington University.
Field Programmable Port Extender (FPX) 1 Remote Management of the Field Programmable Port Extender (FPX) Todd Sproull Washington University, Applied Research.
Introduction to the FPGA and Labs
Lab 4 HW/SW Compression and Decompression of Captured Image
Modular Design Techniques for the FPX
Lab 1: Using NIOS II processor for code execution on FPGA
The 8085 Microprocessor Architecture
Chapter 8 ARP(Address Resolution Protocol)
Lecture 15 PicoBlaze Overview
ARP and RARP Objectives Chapter 7 Upon completion you will be able to:
Dr. Michael Nasief Lecture 2
CprE / ComS 583 Reconfigurable Computing
An Introduction to Microprocessor Architecture using intel 8085 as a classic processor
Washington University
Washington University
Lecture 14 PicoBlaze Overview
Lecture 16 PicoBlaze Overview
Demonstration of a High Performance Active Router DARPA Demo - 9/24/99
FPro Bus Protocol and MMIO Slot Specification
ECE 448: Lab 6 Using PicoBlaze Fast Sorting Class Exercise 2.
Hello Bob – An example application for the FPX
Washington University, Applied Research Lab
Remote Management of the Field Programmable Port Extender (FPX)
Layered Protocol Wrappers Design and Interface review
♪ Embedded System Design: Synthesizing Music Using Programmable Logic
Presentation transcript:

The FPX KCPSM Module 1 Henry Fu The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the FPX Henry Fu Washington University Applied Research Lab Supported by: NSF ANI and Xilinx Corp.

The FPX KCPSM Module 2 Henry Fu Motivation Hardware plugins are well suited for processing data with high throughput Software plugins are well suited for implementing complex control functions  Need a hybrid plugins that can implement complex control functions with high data throughput

The FPX KCPSM Module 3 Henry Fu Introduction The FPX KCPSM module is a hardware plugin that executes software on an embedded soft- core processor It implements active networking functions on the FPX using both hardware and software It includes circuits to be reprogrammed over the network and to execute new programs between the processing of data packets

The FPX KCPSM Module 4 Henry Fu Overview The FPX KCPSM Module is composed of three parts: –The KCPSM, a 8-bit microprocessor developed by Xilinx Corp. –The Protocol Wrappers, a circuit used to simplify the processing of ATM cells, AAL5 frames, IP packets, and UDP datagrams –The Interface, a circuit used to interconnect the KCPSM and the Protocol Wrappers

The FPX KCPSM Module 5 Henry Fu The FPX KCPSM Module KCPSM DATA MEMORY PROGRAM MEMORY ADDRINST INTERFACE D_MOD_IN CONTROL ADDRDATA PROTOCOL WRAPPERS INSTADDRPORT_ID BUS I/O BUS UDP PACKETS ATM CELLS D_OUT_MOD CONTROL SIGNALS UDP PACKETS ATM CELLS ENABLE_LREADY_L SOC_MOD_IN TCA_MOD_IN SOC_OUT_MOD TCA_OUT_MOD D_OUT_MODD_MOD_IN CLK RESET_L SIGNALS

The FPX KCPSM Module 6 Henry Fu Features Software can be loaded over the network through the use of UDP datagrams Up to four data packets and up to two programs can be stored in the module at a time  The processing function can be changed dynamically, on a packet by packet basis

The FPX KCPSM Module 7 Henry Fu Background of the FPX The FPX (Field Programmable Port Extender) –A reprogrammable logic device that provides a hardware platform to deploy network modules –It is composed of two parts: NID (Network Interface Device), a circuit that interconnects the WUGS (Washington University Gigabit Switch), the line cards, and the RAD RAD (Reprogrammable Application Device), a circuit that can be reprogrammed to hold user-defined network modules

The FPX KCPSM Module 8 Henry Fu Configuration of the FPX The FPX acts as an interface between the line cards and the WUGS IPP OPP IPP OPP Card OC3/ OC12/ OC48 Line FPX Extender Port programmable Field- FPX Extender Port Field- programmable Card OC3/ OC12/ OC48 Line Switch Fabric Gigabit

The FPX KCPSM Module 9 Henry Fu Major Components of the FPX KCPSMLoopback

The FPX KCPSM Module 10 Henry Fu Background of the KCPSM The KCPSM (Constant (K) Coded Programmable State Machine) –A 8-bit microcontroller –Consumes only 35 CLBs in FPGA –Provides 49 different instructions, 16 registers, 256 directly and indirectly addressable ports, and a maskable interrupt –Runs at a maximum frequency of 70 MHz –Developed by Ken Chapman of Xilinx Corp.

The FPX KCPSM Module 11 Henry Fu Background of the KCPSM (More) The KCPSM –Designed for Xilinx Virtex and Spart-II devices –Provided in the form of an EDIF macro –Included an assembler and debugger INPUT [7:0] INTERRUPT OUTPUT [7:0] PORT_ID [7:0] READ_STROBE WRITE_STROBE CLK ADDR [7:0]INST [15:0] KCPSM

The FPX KCPSM Module 12 Henry Fu Downloading the KCPSM Package The KCPSM Package from Xilinx Corp. –Visit –Left click on the KCPSM package –Open the ZIP file –Extract to h:\xilinx –Start Cygwin Bash Shell Engineering > FPGA Tools > Cygwin Bash Shell cd /cygdrive/h/xilinx/

The FPX KCPSM Module 13 Henry Fu Contents of the KCPSM Package Access the KCPSM Package –An assembler called KCPSMBLE./KCPSMBLE debug.psm –An debugger called PSMDEBUG./PSMDEBUG debug.coe –Documentations A modified KCPSM package that includes example programs will be included as part of the FPX KCPSM package during the exercise

The FPX KCPSM Module 14 Henry Fu Background of the Protocol Wrappers The Protocol Wrappers –A circuit that streamline the networking functions to process ATM cells, AAL5 frames, IP packets, and UDP datagrams –A layered design that consists different processing circuit in each layer –Allows application to be implemented at a level where important details are exposed and irrelevant details are hidden

The FPX KCPSM Module 15 Henry Fu Overview of the Protocol Wrappers The Protocol Wrappers is composed of four circuits: –Cell Processor processes raw ATM cells between network interfaces –Frame Processor processes variable length AAL5 frames –IP Processor processes IP packets –UDP Processor sends and receives UDP datagrams

The FPX KCPSM Module 16 Henry Fu Overview of the Protocol Wrappers (More) UDP Processor IP Processor Cell Processor Frame Processor Data Output Data Input Application-level Hardware Module Interfaces to Off-Chip Memories

The FPX KCPSM Module 17 Henry Fu Downloading the Wrappers Package The Protocol Wrappers Package –Visit –Right click on the Wrappers Package –Save it to h:\ –Start Cygwin Bash Shell Engineering > FPGA Tools > Cygwin Bash Shell cd /cygdrive/h/ gunzip wrappers.tar.gz tar xvf wrappers.tar

The FPX KCPSM Module 18 Henry Fu Contents of the Protocol Wrappers Package Access the Protocol Wrappers Package –Cell Processor cellwrapper.vhdl, the VHDL instantiation file cellproc_sim.vhd, the VHDL simulation file cellproc.edn, the EDIF Macro synthesis file –Frame Processor framewrapper.vhdl, the VHDL instantiation file frameproc_sim.vhd, the VHDL simulation file frameproc.edn, the EDIF Macro synthesis file

The FPX KCPSM Module 19 Henry Fu Contents of the Protocol Wrappers Package –IP Processor ipwrapper.vhdl, the VHDL instantiation file ipproc_sim.vhd, the VHDL simulation file ipproc.edn, the EDIF Macro synthesis file –UDP Processor udpwrapper.vhdl, the VHDL instantiation file udpproc_sim.vhd, the VHDL simulation file udpproc.edn, the EDIF Macro synthesis file –COREGEN Components

The FPX KCPSM Module 20 Henry Fu Overview of the Interface The Interface –A circuit that interconnects the KCPSM and the Protocol Wrappers –Switches the source and destination IP address and UDP port numbers, buffers the incoming UDP packets and stores them to the memory, resets the KCPSM, and writes the outgoing UDP packets back to the sender

The FPX KCPSM Module 21 Henry Fu Overview of the Interface (More) The Interface is composed of seven control units: –UDP Packets Header Switch –UDP Packets FIFO Control –UDP Packets Type Check –UDP Packets Store Control –KCPSM Reset Control –Unmodified Program Packets Echo Control –Completed Data Packets Write Control

The FPX KCPSM Module 22 Henry Fu Overview of the Interface (More) FIFO Program Memory Data Memory KCPSM Packet Program Unmodified Packet UDP ADDRINSTADDRDATA Control SignalsPacket UDP Packet UDP Packet Control Signals Control Signals Completed Data Packet Program Packet Data Packet Write Grant Signals Control Buffered UDP Packets Header Switch UDP Packets Type Check UDP Packets FIFO Control UDP Packets Store Control Data Packets Write Control Reset Control KCPSM Program Pkts Echo Control UDP Packet

The FPX KCPSM Module 23 Henry Fu Overview of the Interface (More) FIFO Program Memory Data Memory KCPSM Packet Program Unmodified Packet UDP ADDRINSTADDRDATA Control SignalsPacket UDP Packet UDP Packet Control Signals Control Signals Completed Data Packet Program Packet Data Packet Write Grant Signals Control Buffered UDP Packets Header Switch UDP Packets Type Check UDP Packets FIFO Control UDP Packets Store Control Data Packets Write Control Reset Control KCPSM Program Pkts Echo Control UDP Packet

The FPX KCPSM Module 24 Henry Fu UDP Packets Header Switch Control –Switches the source and destination IP address and UDP Port numbers of the UDP packets –Allows the unmodified program packets and completed data packets to be echoed back to the sender

The FPX KCPSM Module 25 Henry Fu UDP Packets FIFO Control –Buffers incoming UDP packets –Delays the arrival of the UDP packets to the UDP Packets Store Control so that it can wait for the result from the UDP Packet Type Check in order to determine whether to store the UDP packets into the program memory or into the data memory

The FPX KCPSM Module 26 Henry Fu UDP Packets Type Check –Determines if the incoming UDP packets is a program packet or a data packet –Inspects the first word of the UDP payload –0x indicates a program packet –0x indicates a data packet

The FPX KCPSM Module 27 Henry Fu UDP Packets Store Control –If the incoming packet is a program packet Stores the UDP payload, except the first word, into the program memory –If the incoming packet is a data packet Stores the whole packets, including the ATM, AAL5 Frame, IP and UDP headers, the UDP payload, and the ATM trailers into the data memory –Increments the bank counters so that the next UDP packet will store into the next available bank of memory

The FPX KCPSM Module 28 Henry Fu KCPSM Reset Control –Resets the KCPSM by asserting the Interrupt input of the KCPSM for two clock cycles –If there is no new program loaded Resets the KCPSM so that it processes the next available data packets using the current program –If there is a new program loaded Resets the KCPSM and increments the program counter so that it processes the next available data packets using the new program

The FPX KCPSM Module 29 Henry Fu Unmodified Program Packets Echo Control –Echoes the incoming program packets back to the sender –Passes any non-UDP packets through the module

The FPX KCPSM Module 30 Henry Fu Completed Data Packets Write Control –Writes the completed data packets back to the sender only if they have been processed by the KCPSM there is no new incoming data packet by inspecting the WR_GRANT signal from the UDP Packets Store Control

The FPX KCPSM Module 31 Henry Fu The FPX KCPSM Module Demo Network Data Compression using RLE (Run- Length Encoding) Algorithm –Compression example: ‘AAAABBBC’ compresses to ‘A4B3C’ –Decompression example: ‘A4B3C’ decompresses to ‘AAAABBBC’ –Allowed input characters range from ‘A’ to ‘Z’, ‘a’ to ‘z’

The FPX KCPSM Module 32 Henry Fu The FPX KCPSM Module Demo (More) Log on to fpx.arl.wustl.edu / fpx2.arl.wustl.edu using SSH (Secure Shell) fpx / fpx2 is connected to the line cards / fpx boards / WUGS fpx / fpx2 directs network traffic to the line cards / fpx boards / WUGS IP over ATM is configured on fpx / fpx2 to send UDP packets on VCI / VPI #96

The FPX KCPSM Module 33 Henry Fu The FPX KCPSM Module Demo (More) A C program called UDPTEST is executed on the fpx / fpx2 and is used to send program packets to the FPX KCPSM module –Download URL: –Usage:./UDPTEST RLEEN.TBP (Encoder)./UDPTEST RLEDE.TBP (Decoder) –The file contains the raw machine code of the KCPSM program

The FPX KCPSM Module 34 Henry Fu Program Packet Processing KCPSM INTERFACE ProgramPacket Program PROGRAMMEMORY BANK ALTERNATECURRENT Independent Process INSTADDR INST program packet there is new incoming Proceed as long as there is new incoming program packet

The FPX KCPSM Module 35 Henry Fu The FPX KCPSM Module Demo (More) A C program called UDPSTR is executed on the fpx / fpx2 and is used to send data packets containing character strings to the FPX KCPSM module –Download URL: –Usage:./UDPSTR [-h hostname] [-p destination port] –Enter the character strings in the input prompt

The FPX KCPSM Module 36 Henry Fu Data Packet Processing KCPSM DataPacket MEM DA TA ORY BANK ALT Data Packet ADDR ALTCUR INTERFACE DATA BUS ADDRDATA BUS ADDRI/O BUS Proceed as long as there is data packet incoming data packet there is new Proceed as long as and no new incoming data packet there is completed data packet Proceed as long as

The FPX KCPSM Module 37 Henry Fu The FPX KCPSM Module (Demo) Screenshot of the compression example:

The FPX KCPSM Module 38 Henry Fu The FPX KCPSM Module Demo (More) Screenshot of the decompression example:

The FPX KCPSM Module 39 Henry Fu Synthesis Results The FPX KCPSM Module is synthesized to a Xilinx XCV1000E-7-FG680: –Maximum Frequency: 70 MHz –Chip Utilization: 35% (4305 / slices) –External Input Buffers: 69 uses –External Output Buffers: 105 uses –Total LUTS: 3807 uses

The FPX KCPSM Module 40 Henry Fu Synthesis Results (More) The Xinlinx backend synthesis script: –ngdbuild -p xcv1000e-7-fg680 -uc design.ucf –map -p xcv1000e-7-fg680 -o top.ncd design.ngd design.pcf –par -w -ol 2 top.ncd design.ncd design.pcf –trce design.ncd design.pcf -e 3 -o design.twr -xml design_trce.xml –bitgen design.ncd -b -l -w -f bitgen.ut

The FPX KCPSM Module 41 Henry Fu Conclusion The FPX KCPSM Module –Demonstrates how to embed a softcore processor and how to use the Protocol Wrappers in an FPX module –Combines software flexibility and hardware performance into a hybrid module –Targets to work with the KCPSM, WUGS, FPX research environment, but can easily be changed to work with any FPGA-based system