SUPERB TRIGGER …. A. BUDANO – INFN ROMA 3 ON BEHALF OF ROMA1, ROMA3, LNF, NA 2 nd SuperB Collaboration INFN-LNF December 2011

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Let’s remember the specs in SuperB : re-implement BaBar L1 trigger with some improvements Shorter latency (~6  s instead of 12  s) Higher sampling frequencies (DCH and EMC) 2-d map for calorimeter Possible additions SVT trigger Bhabha Veto Do we need an absolute time stamp at the trigger level? Challenge To keep the event loss due to dead time below 1% => a maximum of ~60ns “per-event dead time” is allowed in trigger and FCTS. This requirements pushes for trigger time resolution of about ns it could be hard to reach. This requested has been partly eased. Latest studies from D. Breton slides S. LUTZ kHz Exponential Inter-arrival time pdf.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 BaBar: Trigger Layout J. C. Andress et Al., “BaBar Calorimeter Level 1 Trigger Design”, BaBar Note (1998)

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Calorimeter trigger (requirements)  It works independently from the DC trigger.  It’s based on the topology of the energy deposits.  We would like to have an architecture similar to DC in order to use the same HW.  As in the case of DC one it should have a shorter latency and a good trigger time resolution (about ns).

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 What we learnt from CsI  Different measures in different conditions on single crystals ruled out the possibility to use PiN diodes or even APD. The measured resolution spanned from 30 to 50 ns. See P. Branchini London or this report from V. Bocci.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 What about the detectors?  We have learnt that SVT DAQ window is 300 ns. Still demanding but not so bad. The limit is the intrinsic jitter of the sub-detector.  For the DC the DAQ window is about 1  s.  The minimum DAQ window belongs to IFR and it is 150 ns (desired) 100 ns (is the real minimum).

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 SuperB EMC EMC Barrel : 5760 CsI(Tl) Crystals EMC Forward = 4400 Lyso Crystals (176 modules) For the moment there are different options for the forward EMC. Lyso is to be considered a case study.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC Topology  There are several mechanical constraints from barrel EMC this implays 9 degree modularity for the EMC (3 crystals in .  The  at the calorimeter covered by each card reading the DC had better match with the calorimeter  granularity. 48 channels reading a supercell would imply a coverage of 36 degrees.  Each DC FE TSF treats the signal from 48 or 64 channels (this matches the DC FE board). 480 towers from the Barrel EMC

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Double Range shaper CSP  Pulse Encoder LVDS Analog Range (0,1) n Trigger Fast Path X N cryst Energy accurate measurement path Parallel readout SiPm? this part should be rad-hard (to be investigated). EMC fast trigger and energy paths

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Let’s follow the trigger path 480 LVDS link in the barrel EMC. The information Stored is the «trigger time assertion» and energy in the width of the signal. An LVDS like signal driven by an actel could be good candidate to do That, if a better solution cannot be found. Concentrator: Link reduction stage To trigger crates Here we could be far enough or even shielded from radiation. Moreover this link reduction is not strictly necessary.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC possible trigger crate layout CPUCPU M A S T E R 0 EM1EM2EM3 EM10EML9 M A S T E R L M A S T E R EM1 from 1 to 10 have The  image of the barrel EMC. The Master(s) have the Full EMC informations. Possibly far from detector. We should not have problems from radiation. We are studying the possibility to use  TCA as a backplane.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC trigger algorithm (BaBar)  Tower energy was added in  bins over the entire barrel.  A Y sum over the two rearmost tower in the barrel was defined.  A X sum for the forward end-cap. Each of these sum was then compared with an energy threshold corresponding to:  E clu > GeV (Minimum ionizing M cluster)  E clu > GeV (E Cluster)  E clu > 0.5 GeV (G cluster)  E clu > GeV (X cluster forward end-cap)  E clu > 2.0 GeV (Y cluster backward end-cap)

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC and DC Trigger criteria

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC Open problems:  Shorter latency  trigger time jitter (in BaBar 1  s) area aiming at some 10 ns. As long as latency is concerned: It’s conditioned by the trigger strategy exploited, Moreover in BaBar it was 7.2  s.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Barrel CsI (Tl doped) original BaBar 3 thresholds applied to the signal of the tower. A FIR Filter with 8 parameters was applied to the signal. Its zero crossing occurred at roughly a fixed time distance from the start of the signal, it was used to gate the threshold information. Due to this mechanism the time resolution was hundreds of ns. P. D. Dauncey et Al., “Design and performance of the level 1 calorimeter trigger for the BABAR detector” (2001) The plot shows the difference between the EMC trigger time and the DC trigger time.  +  - events used to select good resolution in DC.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 EMC BaBar strategy for trigger assertion comments  Trigger latency was 7.2  s, 6  s seems reachable with this approach.  It turned out the the 1  s maximum trigger time jitter was NOT dominated by the detector. Nevertheless a contribution spanning from 30 ns to 50 ns is has been measured.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 SiPM Front End Electronics for tbeam Each board read 8 channels splits the signal to be read by a QDC and a TDC. We’ll use the setup to measure the time resolution of the CsI (tl doped) crystal. The master set thresholds and the SiPm voltages.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 BaBar/SuperB DC sketch In SuperB all stereo layers in between U2 and V9. Moreover A1 has 8 radial wires rather than 4. From the trigger point of view We could divide A1 in 2 superlayers and have 11 equivalent SLs structure.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 DC SuperB present-1 design SL1SL2SL3SL4SL5SL6SL7SL8SL9SL10TOT Planes TypeAUVUVUVUVA #wires172*4 204* * * * * * * * * * #TSF 48 opt #NBCD 48 opt /2 15 #TSF 64 opt #NDCB 64 opt 1/ /11 Number of wire could increase due to internal radius uncertainties. The 48 vs 64 depends on the form factor of the FE board used at the moment a conservative assumption has been made (i.e. 6U VME form factor)

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 BaBar Strategy

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Super B detector 8056 wires from DC FE crate SL1 FE crate SL2 FE crate SL3 FE crate SL4 FE crate SL5 FE crate SL6 FE crate SL7 FE crate SL8 FE crate SL9 FE crate SL wires from DC 472 wires from DC 536 wires from DC 600 wires from DC 664 wires from DC 728 wires from DC 792 wires from DC 856 wires from DC 920 wires from DC 984 wires from DC DC SuperB present design 246 wires on SL10 is not what we would like to match the EMC sector in  would be better because in this case we would have 40 cells a perfect match with 9 degree EMC sector.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 FE crate Super layer 10 CPU DC FRONT END Discriminator DC FRONT END Discriminator DC FRONT END Discriminator ethernet link 64 channels copper/optical link Test Discriminator Input signals from DC front end discriminated signals In SuperB the discriminator board becomes a mez card and can be upgraded in order to compute TSFs and deliver them through a copper or optical link if there are radiation problems. Otherwise the «standard» solution would be welcome. DC SuperB present design

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 RF emulator  We have also built a ring oscillator to emulate RF when a machine trigger occurs.  And a transition board to feed Virtex6 demo board with LVDS signals.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Track Segment Finder (TSF)  The problem of this trigger module is to find the best track segment(s) in the monitored supercell. A rad tollerant actel could do the job.  In BaBar the signal delivered from each single wire was sent to a discriminator sampled ad 3.7 MHz. Hits were then broadcasted to the TSFs (24 same strategy would imply 64 links in SuperB) through optical links.  In SuperB we might have an higher sampling to improve the trigger time resolution. Nevertheless since we have 132 sources (worst case) the link we could use needs in principle a low bandwidth. Let’s take for example a 14.8 MHz sampling. Each link delivers the information of 64 wires to the DC trigger crate. So the bandwidth is:14.8MHz*64 = 947 Mbit/s. I think a more robust though less performant link could be enough if a better «rad hard» solution can’t be found. This link in principle could avoid using lasers and photon detector.  we could also integrate the TSF on the FE DC crates. This allows us to shrink latency. A higher sampling could be allowed and in principle even a clockless discriminator could be used. The trigger time jitter, PT and zed coordinate measurement should in principle benefit from that. We will study the 2 options exploiting the LNF prototype.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 TSF (Track Segment Finder) P P P P 4 pattern for a fixed pivot tube. The other 4 pattern can be found via a parity transformation. So in this example there are 8 patterns per pivot tube and 4 pivot tubes. In total 32 combinations. 5 bits are enough to code the info MHz sampling means 74 Mbit/s link.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 CellT Track 1Track 2Track 3 CellT Track 1Track 2Track 3 BaBar SuperB in this example sampling is twice the BaBar one TSF (Track Segment Finder)

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Track finding BLT Kinoshita in BaBar

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 TSF (trigger time jitter in BaBar) With this strategy we are dominated by the sampling frequency Trigger criterion:1.5 track In Babar 3 strategies were examined. 1) First tick with 1.5 tracks present. 2) Last tick with 1.5 tracks present. 3) Last tick with 4 out of four segments. Different latency and trigger jitter time were determined.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 What could be done (if necessary) From BaBar note /8/1996 Weight each track segment latency with its own error. Apply a weighted average on all the gathered TSFs Sigma is about 14.8 ns when sampling at 3.7 MHz and 10 when sampling at 7.4 MHz We could use an Hw processor on the trigger crate to implement this algorithm. A drawback: the precision depends on TSF number: physics of the final state

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 FE crate Super layer 10 CPU DC FRONT END Discriminator DC FRONT END Discriminator DC FRONT END Discriminator ethernet link 64 channels copper/optical link FE crate Super layer 1 CPU Trigger crate Master TSF SL5TSF SL4TSF SL3TSF SL2TSF SL1TSF SL6TSF SL7TSF SL8TSF SL9 TSF SL10 ethernet link CPU DC FRONT END Discriminator DC FRONT END Discriminator DC FRONT END Discriminator ethernet link 64 channels copper/optical link Link sl10Link sl1 Link sl9 Link sl8 Link sl7 Link sl6 Link sl2 Link sl3 Link sl4 Link sl5 DC trigger crates possible layout

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 Binary Track Linker Pt and z measurement Up to 24 optical links (TSF) per board. This topology can implement Kinoshita directly on the crate to find a track. Moreover the Masters have the full DC info and therefore can implement kinoshita with any granularity and compute PT and z measurements. CPUCPU M A S T E R 0 SL1SL2SL3 SL10SL9 M A S T E R L M A S T E R SL1 has 8 radial wires in the Present design. Should we not manage to cast them in a single Board we could cast it in 2 boards.

A. Budano - INFN Roma nd SuperB Collaboration INFN-LNF, December 2011 A possible sketch of trigger system in SuperB DC and EMC trigger crates have a common inteface (LVDS or optical) with pertaining sub-detectors. EMC(i) and DC(i) boards share a common hw platform and only differ in firmware.