ICT 1 Pixel 2008 International Workshop, FNAL September 23-26, 2008 T. E. Hansen a, A. Kok a, C. Da’Via b, T. A. Hansen a, J. Hasi b, C. Kenney d, N. Lietaer a, M. Mielnik a, S. Parker c, P. Storås a a SINTEF MiNaLab, Norway b The University of Manchester, UK c The University of Hawaii, USA d Molecular Biology Consortium, USA First fabrication of full 3D-detectors at SINTEF

ICT 2 Outline Motivation for 3D-detector activity and SINTEF involvement Technology issues Results from first SINTEF 3D-run Further developments and next run

ICT 3 Device configuration Full 3-D Structure with active edges 3-D silicon detectors proposed by S. Parker in 1995 Active edge proposed by C. Kenney in 1997 n - and p - electrode holes penetrating through chip. Completely filled with doped poly-silicon Silicon chip (200 to 300 µm thick) p – active edge trench filled with doped poly-silicon So far this configuration has only been made at Stanford

ICT 4 Motivation for 3D-detectors Advantages of 3D-detectors Low pre-irradiated depletion voltage Fast time response Edgeless capability (active edge), no dead area due to broad guard ring areas Non surpassed radiation hardness Motivation for SINTEF to get involved SINTEF joined 3D-collaboration in Part of effort to transfer 3D technology to affordable(?) small and medium scale production Processing line adapted to detector fabrication. Experience in detector technology since early 1980ties Number of in-house state-of-art Deep Reactive Ion Etchers (DRIE) Long experience in 3D silicon micromachining

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6 Fundamental Tool for 3D - Detectors: Deep Reactive Ion Etcher (DRIE) Tools at SINTEF: AMS200#1 AMS200# 2 AMS200 ISPEEDER “DIRTY HARRY” “ OLDBOY” “IPROD” State-of-art Alcatel ICP tools Bosch process with subsequent etching and deposition of polymer “Old boy” and “IPROD” with robot “IPROD” (Alcatel AMS 200 ISPEEDER) commissioned beginning of To be used for next 3D detector run. About 4x throughput compared to “Old Boy” used in first run. Can be operated with both low and high frequency chuck bias. Low frequency bias reduces and/or removes notching problems

ICT 7 SINTEF poly-silicon process not suited for hole filling SINTEF LPCVD process restricted to poly-silicon films ≤ 1 µm Electrodes could be filled at SINTEF by sequential depositions of 1 µm films. 70 hrs machine time, not a production approach. SINTEF first 3D detector prototype run 1 µm poly-silicon deposition and doping made at SINTEF. Subsequent electrode filling and doping done at Stanford Approach for future production runs Find industrial sub-contractor Invest 450 k€ in LPCVD deposition tool made by Centrotherm (D). Said capability deposition of 20µm poly-silicon on 50 wafers in 5 hours. Demonstration facility planned at Univ. of Hanover, but not realized so far. First installation at VTT in Finland? Second critical process in full 3D fabrication: Poly-silicon Electrode and Trench Filling

ICT 8 First 3D development run at SINTEF Started mid December 2006, completed February Included several process developments Original photo mask design by Chris Kenney with Atlas pixel layout, slightly modified by SINTEF N-type wafers, 4-inch, 250 µm thick, specific resistivity 1500 to 2000 Ωcm. Not optimal configuration for n- readout as active edge is part of total chip pn-junction Calculated depletion voltages StructureInter electrode distance Full depletion voltage 4E56 µm≤ 7.5 V 3E74 µm≤ 13 V 2E106 µm≤ 27 V

ICT 9 ATLAS 3-D Pixel – Wafer Layout Designed by C Kenney, modified at SINTEF Main ATLAS pixel, 2E, 3E, 4E ATLAS pixel test chips Various test chips including baby strip detectors

ICT 10 ATLAS pixels – 4E, 3E, 2E 4 or 7 µm trench (active edge) 14µm holes 4 electrodes per pixel – 4E 3 electrodes per pixel – 3E 2 electrodes per pixel – 2E n-readout electrodes p-bias electrodes

ICT 11 Main fabrication steps Modification of Stanford Process (S. Parker, C. Kenney) IEEE Trans Nucl Sci 464 (1999) 1224 IEEE Trans Nucl Sci 482 (2001) 189 P-spray implant Oxidation Wafer bonding 2 DRIE steps 2 Poly-silicon deposition steps Readout Electrodes Readout Electrodes Bias Electrodes and Trenches Bias Electrodes and Trenches RIE poly-silicon back etch Contact holes MetalPassivation 7 layers of photolithography Readout electrodes Bias electrodes Doped poly Support wafer Oxide Metal Passivation

ICT 12 Use of Aluminium Mask for DRIE etching Based on experience it was decided to use aluminum masking for DRIE etching. Before plasma etch of polymerAfter plasma etch of polymer

ICT 13 Before process tuning Damage at top, Notching at bottom After process tuning No damage No notching at bottom Several iterations of DRIE process tuning on AMS 200 (“Old Boy”) machine for 3D process – Long delay Oxide and support wafer

ICT 14 DRIE Result – Trenches/ Active Edge “Old Boy” after process tuning 7 µm trenches Detail at top Polymer

ICT 15 Electrodes after last poly-silicon filling Void

ICT 16 Wafer stress and bow – almost show stopper Wafer under stress after 2. polysilicon filling Bows at a curvature 10 times larger than a standard wafer Incompatible with handling by robotic tools. Wafer breakage Bending makes mask alignment inaccurate and difficult 3D wafer after polysilicon filling Standard silicon wafer

ICT 17 Opening of p- and n- electrode contacts on n-readout wafer using electrode photo mask. Both contacts opened Opening of p-electrode contacts: Well aligned Opening of n-electrode contacts: Misaligned, but not critical on n-substrate

ICT 18 Topography of electrodes 3.5µm deep

ICT 19 ALTAS 2E chip – measurement of total leakage current Two electrodes per pixel, ~ 2700 pixels All p electrodes plus active edge connected. Measurement on one pixel shows total chip leakage current µA Breakdown Depletion

ICT 20 ALTAS 3E chip – average pixel leakage current calculated from measurement of total leakage current – 2700 pixels

ICT 21 ALTAS 4E chip – average pixel leakage current calculated from measurement of total leakage current – 2700 pixels 4 different chips

ICT 22 Inter pixel / strip resistance Measured between n-electrodes in neighbouring pixels/strips at 60 V 4E structures: MΩ 3E structures: MΩ 2E structures: MΩ Baby strip: GΩ

ICT 23 Summary of results from first SINTEF 3D-run 11 wafers consumed in different process development steps. 7 wafers broke due to built in stresses. 2 intact wafers with n-readout devices Both wafers show acceptable diode characteristics Typical average leakage current corresponds to nA per pixel measured at 30 V. When interpreting results note that probe testing on single pixel picks up total chip leakage current including active edge. May include leaky pixels and edges Breakdown voltage 60 to 100 V One wafer sent to IZM for bump bonding. 10 chips bump bonded to FEI-3 read out chip. Bump bonding failed on 8 chips 2 surviving chips show reasonable electric behaviour in initial tests at CERN and see particles from radioactive sources (September 25, 2008)

ICT 24 Second 3D-run at SINTEF N - readout devices on p-wafers. P-doped active edge acts as depletion stop and not part of pn-junction. More robust! Wafer specifications 1.Based on experiences from first run focus on  Reduce wafer stress and bow to improve lithography and reduce breakage  Improve on topography 2.New AMS 200 ISPEEDER to be used for DRIE etching 3.Mask design in progress including ATLAS, CMS and Medipix type devices 4 - inch Depl. Voltage 200 or 285 µm4E3E2E ≥ Ωcm≤ 3.5 V≤ 6 V≤ 12 V

ICT 25 Tuning of AMS 200 ISPEEDER “IPROD” for next SINTEF 3D – run 14 µm holes through 320 µm thick wafer bonded to support wafer in 40 min etch time Etch stop against oxide with no notching 14 µm hole 320 µm wafer support wafer Detail at bottom Etch stop at oxide with no notching

ICT 26 PRELIMINARY MASK LAYOUT FOR 2 nd RUN as per September 10, 2008 Lot of free space available! 1E, 2E, 3E, 4E, 5E test structures Medipix chips ATLAS 1E, 2E, 3E, 4E, 5E chips Area reserved for CMS type structures. Reserved 15% of wafer area (only 4% shown)

ICT 27 Thank you for your attention!