CHAPTER 14 Digital Systems

Figure 14.1 RS flip-flop symbol and truth table Figure

Timing diagram for the RS flip-flop Figure

Figure 14.4 The RS flip-flop with enable, preset, and clear lines: (a) logic diagram, (b) timing diagram, (c) IC schematic Figure

Figure 14.5 Data latch and associated timing diagram Figure

Figure 14.6 The D flip-flop: (a) functional diagram, (b) symbol, (c) timing waveforms, and (d) IC schematic Figure

Figure 14.7 The JK flip-flop: (a) functional diagram, (b) device symbol, and (c) IC schematic Figure

Truth table for the JK flip-flop Figure Figure 14.8

Figure Binary up counter functional representation, state table, and timing waveforms Figure

Figure Decade counter: (a) counting sequence; (b) functional diagram; and (c) IC schematic Figure

Figure Ripple counter Figure

Figure Three-bit synchronous counter Figure

Figure Ring counter Figure

Figure A 4-bit parallel register Figure

A 4-bit shift register Figure

Figure A 3-bit binary counter and state diagram Figure

Table State transition table for modulo-4 up-down counter

State diagram of a modulo-4 up-down counter Figure

Figure Karnaugh maps for flip-flop inputs in modulo-4 counter

Implementation of modulo-4 counter Figure

Figure Structure of a digital data acquisition and control system

(a) High-level block diagram of microcontroller; (b) internal organization of microcontroller Figure