CHAPTER 11 LATCHES AND FLIP-FLOPS This chapter in the book includes: Objectives Study Guide 11.1Introduction 11.2Set-Reset Latch 11.3Gated D Latch 11.4Edge-Triggered D Flip-Flop 11.5S-R Flip-Flop 11.6J-K Flip-Flop 11.7T Flip-Flop 11.8Flip-Flop with Additional Inputs 11.9Summary Problems

Spring 2004Digital System2 Objectives 1.Explain in words the operation of S-R and gated D latches 2. Explain in words the operation of D, D-CE, S-R, J-K and T flip-flops 3. Make a table and derive the characteristic (next-state) equation for such latches and flip-flops. State any necessary restrictions on the input signals 4. Draw a timing diagram relating the input and output of such latches flip-flops 5. Show how latches and flip-flops can be constructed using gates. Analyze the operation of a flip-flop that is constructed of gates and latches

Spring 2004Digital System3 Flip-Flops (FF) Sequential switching networks output depends on both present inputs and past sequence of inputs Flip-Flops are most commonly used memory devices Flip-Flops assume one of two stable output states has one or more inputs which can cause the output state to change

Spring 2004Digital System4 Feedback output of one gate is connected back into the another gate's input so as to form a closed loop needed to construct a switching circuit which has a memory Inverter with feedback oscillate back and forth between 0 and 1 never reach a stable condition oscillation rate is determined by the inverter's propagation delay

Spring 2004Digital System5 11.1Introduction Fig  Stable state Two inverters with feedback two stable conditions – stable states

Spring 2004Digital System6 S-R(Set-Reset) Flip-Flop can make a simple F/F by using a feedback Operations : S=R=0, Q=0, P=1? stable? yes becomes S=1 S=1, R=0 P=0, Q=1 S=0 again. Then? P=0, Q=1 R=1 – Q=0, P=1 R=0 : go back to first Two different stable state for a given set of inputs R=S=1 을 허용하지 않으면 항상 P=Q’

Spring 2004Digital System7 SR F/F : cross-coupled structure To emphasize the symmetry, SR F/F is often drawn in cross-coupled form Q 가 R 이 입력인 NOR gate 의 출력이지만 기호는 Fig 11-5 처럼 사용 S-R latch

Spring 2004Digital System8 Improper Operation What if S=R=1? P=Q=0 violate basic F/F rules (F/F outputs to be complements) oscillate if the gate delays are exactly equal

Spring 2004Digital System Set-Reset Latch Fig Timing Diagram for S-R Latch Table S-R Latch Operation Inputs not allowed ε : response time or delay time of the latch S R Q Q 

Spring 2004Digital System Set-Reset Latch Fig Map for next-state equation or characteristic equation

Spring 2004Digital System11 Switch Debouncing with an S-R Latch

Spring 2004Digital System Set-Reset Latch Fig Latch Inputs not allowed

Spring 2004Digital System Gated D Latch Figure Gated D Latch Figure Symbol and Truth Table for Gated Latch

Spring 2004Digital System Edge-Triggered D Flip-Flop Figure D Flip-Flops Truth table Figure Timing for D Flip-Flop (Falling-Edge Trigger)

Spring 2004Digital System Edge-Triggered D Flip-Flop Given FunctionFigure D Flip-Flop (Rising-Edge Trigger) Figure Setup and Hold Times for an Edge-Triggered D Flip-Flop

Spring 2004Digital System Edge-Triggered D Flip-Flop Figure Determination of Minimum Clock Period

Spring 2004Digital System S-R Flip-Flop Figure S-R Flip-Flop Operation summary : S=R=0 S=1, R=0 S=0, R=1 S=R=1 No state change Set Q to 1 (after active Ck edge) Reset Q to 0 (after active Ck edge) Not allowed Figure S-R Flip-Flop Implementation and Timing

Spring 2004Digital System J-K Flip-Flop Figure J-K Flip-Flop (Q Changes on the Rising Edge) Truth table and characteristic equation

Spring 2004Digital System J-K Flip-Flop Figure Master-Slave J-K Flip-Flop (Q Changes on Rising Edge)

Spring 2004Digital System T Flip-Flop Figure T Flip-Flop Figure Timing Diagram for T Flip-Flop (Falling-Edge Trigger)

Spring 2004Digital System T Flip-Flop Figure Implementation of T Flip-Flop

Spring 2004Digital System Flip-Flops with Additional Inputs Figure D Flip-Flop with Clear and Preset x x 0 0 x x 0 1 x x ,1, x 1 1 (not allowed) Q(no change) Figure Timing Diagram for D Flip-Flop with Asynchronous Clear and Preset

Spring 2004Digital System Flip-Flops with Additional Inputs Figure D Flip-Flop with Clock Enable The MUX output : The characteristic equation :

Spring 2004Digital System Summary (S-R latch or flip-flop) (gated D latch) (D flip-flop) (D-CE flip-flop) (J-K flip-flop) (T flip-flop)