1 CS 352 Introduction to Logic Design Lecture 6 Ahmed Ezzat Latches, Flip/Flops, Registers, and Counters Ch-11 + Ch-12

CS-352Ahmed Ezzat 2 Outline Introduction Set-Reset Latch Gated D Latch Edge-Triggered D Flip-Flop S-R Flip-Flop J-K Flip-Flop T Flip-Flop Flip-Flop with Additional Inputs Registers and Register Transfers – Parallel Adder with Accumulator Shift Registers Design of Binary Counters Counters for other Sequences – Counter Design Using D Flip-Flops Counter Design Using S-R and J-K Flip-Flops

CS-352Ahmed Ezzat 3 Introduction (1) Sequential circuits have the property that the output depends not only on present input but also on the past sequence of inputs. Latches and flip-flops are the basic building block for memory devices. Latch is a memory element that has no clock input, while flip-flop will typically have a clock input. In synchronous digital systems, a common clock synchronize the operation of all flip/flops in a circuit. Switching circuits we studied so far did not have feedback connections (i.e., output of one gate is connected back as input of another gate and form a closed loop. Memory elements expect feedback.

CS-352Ahmed Ezzat 4 Introduction (2) Feedback with oscillations: Feedback with stable states:

CS-352Ahmed Ezzat 5 Set-Reset Latch (1) S: 0  1 (change state)S: 1  0 (no effect) R: 0  1 (change state) Q(t +Є) = S + R’Q(t)

CS-352Ahmed Ezzat 6 Set-Reset Latch (2) The S-R latch have memory as output depends not only on the present inputs but also on the past sequence of inputs. Outputs (P, Q) are always complements (i.e., P = Q’). If S = R = 1, the latch will not operate properly as both P = Q = 0 (P should be complement Q!). If S = R = 0, then we will have oscillations if the gate delays are equal.

CS-352Ahmed Ezzat 7 Set-Reset Latch (3) An alternative form of the S-R latch uses NAND gates:

CS-352Ahmed Ezzat 8 Gate D Latch (1) D latch can be constructed from an S-R latch + gates

CS-352Ahmed Ezzat 9 Gate D Latch (2)

CS-352Ahmed Ezzat 10 Edge-Triggered D Flip-Flop (1) D flip-flop has 2-inputs, D (data) and Ck (clock). Ck is identified by the arrowhead on the flip-flop. D flip-flop changes only in response to the clock input, and not to changes in D input. If the flip-flop changes in response to a 0  1 transition on the clock input, we say the flip-flop is triggered on the rising edge of the clock. If the output changes in response to a 1  0 transition, we say the f/f is triggered on the falling edge of the clock (indicated by an inversion bubble on the clock input). The term active edge refers to the clock edge (rising or falling) that triggers the f/f state change. The state of the D f/f after the active clock edge is equal to the input (D) before the active edge.

CS-352Ahmed Ezzat 11 Edge-Triggered D Flip-Flop (2)

CS-352Ahmed Ezzat 12 Edge-Triggered D Flip-Flop (3)

CS-352Ahmed Ezzat 13 Edge-Triggered D Flip-Flop (4) Propagation delay is equal the time between the active edge of the clock and the resulting change in the output. To function properly, input D has to be taken into consideration: – D input need to be held constant for a period of time before (setup time - t su ) and after (hold time - t h ) the active edge of the clock, otherwise behavior is unpredictable. – Propagation delay (t p ) is the time from the clock changes till Q output changes.

CS-352Ahmed Ezzat 14 Edge-Triggered D Flip-Flop (5) Using the above timing definitions, we can calculate the minimum clock period. Assume inverter delay is 2 ns, f/f propagation delay is 5 ns, and t su = 3 ns. t h is not relevant in this calculation

CS-352Ahmed Ezzat 15 S-R Flip-Flop (1) S-R f/f (also known as Master-Slave) is similar to S-R latch in that S = 1 sets Q =1, and R = 1 sets Q = 0. The difference is f/f has input clock, and the f/f output changes only after an active clock edge. Interpretation of Q + is different: for latch, Q + is the value of Q after latch propagation delay, while with f/f, Q + is the value Q assumes after the active clock edge.

CS-352Ahmed Ezzat 16 S-R Flip-Flop (2) S-R can be constructed from two S-R latches and gates. This example uses clock rising edge as the active clock edge.

CS-352Ahmed Ezzat 17 S-R Flip-Flop (3) S-R is similar to the edge-triggered f/f, except the following difference: – For rising edge-triggered f/f, the value of input is sensed at the rising edge of the clock, and input can change while clock is low. – For S-R f/f, if input changes while clock is low, output may be incorrect. – Example: At t 4, S=1, R=0, so P=1 – S  0 at t 5, P still 1  Q =1 on rising edge of the clock – Now assume S=R=0 at t 5, Q should not change but at t 5 it does change? – Only allow S, R to change while clock is high

CS-352Ahmed Ezzat 18 J-K Flip-Flop (1) An extended version of S-R f/f. J-K f/f has 3 inputs (J, K, Ck). J input correspond to S, K corresponds to R, and active edge notion holds. Unlike S-R f/f, J=K=1 is allowed, and the f/f changes state after the active clock edge, i.e., Q changes from 0  1 or from 1  0. +

CS-352Ahmed Ezzat 19 J-K Flip-Flop (2) J-K f/f changes state t p after the rising edge of the clock, assuming J and K have appropriate values. J-K f/f can be realized using two S-R latches in a Master-Slave arrangement. This is similar to S-R f/f except S, R be replaced with J, K, and Q, Q’ outputs feedback into input gates. Only one of S 1 (J.Q’.Clk) and R 1 (K.Q.Clk’) can be 1 at any given time

CS-352Ahmed Ezzat 20 T Flip-Flop (1) Also called Toggle f/f, is typically used in building counters. Most CPLDs and FPGAs can be programmed to implement T f/fs. When T = 1, f/f changes state after the active edge of the clock. When T = 0, no state change occurs.

CS-352Ahmed Ezzat 21 T Flip-Flop (2) At t 2, t 4, T-input is 1, and Q changes after t p of the falling edge of clock. At t 1, t 3, T-input is 0, and clock edge does not cause a change of state. T f/f can be implemented using J-K f/f: Q + = JQ’ + K’Q = TQ’ + T’Q Another way to implement T f/f is using D f/f + XOR gate: Q + = Q T = TQ’ + T’Q +

CS-352Ahmed Ezzat 22 Flip-Flop with Additional Inputs (1) Frequently, f/f will have additional inputs, e.g., set the f/f to some initial state independent of the clock, or clear the f/f, etc. When ClrN, PreN are 1, then D and clock inputs operate in the normal manner. ClrN and PreN are referred to as asynchronous clear and preset inputs.

CS-352Ahmed Ezzat 23 Flip-Flop with Additional Inputs (2) Gating the clock D f/f with clock enable (D-CE symbol) Implementing D-CD using a D f/f and a multiplexer

CS-352Ahmed Ezzat 24 Registers and Register Transfers (1) Register is a set of f/fs with common clock input. Counter is a sequential circuit made of two or more f/fs which change states in a prescribed sequence when input pulses is received. A 4-bit register can be made of 4 D f/fs: 4-bit Register With Clock Enable 4-bit Register Using Gated Clock

CS-352Ahmed Ezzat 25 Registers and Register Transfers (2) Transferring data between registers is a common operation. If En = 1, Load = 1, then data in Register A is enabled into the tri-state bus and is stored in Q after the rising edge of the clock.

CS-352Ahmed Ezzat 26 Registers and Register Transfers (3) The following is 8 D f/fs with tri-state buffers at the output. Buffers are enabled when En = 0.

CS-352Ahmed Ezzat 27 Registers and Register Transfers (4) Parallel Adder with Accumulator Parallel adder with an accumulator can be achieved by adding a register to the adder as follows (adder adds X to Y and store result in the accumulator):

CS-352Ahmed Ezzat 28 Shift Registers (1) A shift register stores binary data that can be shifted left/right when a shift signal is applied. Bits shifted out of the register will be lost.

CS-352Ahmed Ezzat 29 Shift Registers (2)

CS-352Ahmed Ezzat 30 Shift Registers (3) Parallel shift register (can serve as converting parallel In to serial out shifter):

CS-352Ahmed Ezzat 31 Shift Registers (4) Shift register with inverted feedback is called Johnson Counter (circuit that cycles through fixed sequence of states): Primary and secondary state diagrams * Only if initial state is 010, secondary state diagram is in effect

CS-352Ahmed Ezzat 32 Design of Binary Counters (1) Counters covered here are synchronous counters where all f/fs are synchronized by one common clock. Counter using 3 T-F/Fs to count number of clock pulses: – To construct the counter we need to observe inputs to every T f/f? – F/F A change state on every active clock edge – F/F B change state on active clock edge and when A = 1 – F/F C change state on active clock edge and when A = B = 1

CS-352Ahmed Ezzat 33 Design of Binary Counters (2) State Table for Binary Counter  Karnaugh Maps T c = BAT B = A

CS-352Ahmed Ezzat 34 Design of Binary Counters (3) The same counter using D f/fs: easier is to convert T f/f to D f/f by adding and XOR gate: The rightmost XOR can be replaced by an inverter: A 1 = A’ DA = A’ DB = B A = BA’ + B’A DC = C BA = C’BA + CB’ + CA’ + + +

CS-352Ahmed Ezzat 35 Design of Binary Counters (4) Karnaugh Maps are: D C = C’BA + CB’ + CA’D B = BA’ + B’AD A = A’

CS-352Ahmed Ezzat 36 Design of Binary Counters (5) An Up/Down Binary Counter: state diagram and state table State DiagramState Table

CS-352Ahmed Ezzat 37 Design of Binary Counters (6) An implementation for the Up/Down Counter using D f/f and Gates: DA = A (U + D) DB = B (UA + DA’) DC = C (UBA + DB’A’) BTW: when U = 1, D = 0 this reduces to binary UP counter + + +

CS-352Ahmed Ezzat 38 Design of Binary Counters (7) Downloadable Counter: Ld = 1, binary data is loaded into the counter. (MUX selects D in ). Ct = 1, counter is incremented on active edge of clock. Ld = Ct = 1, load overrides count, and data is loaded in counter. Ld = 0, Ct = 1, MUX selects one f/f output, and circuit is equivalent to D f/f counter on Page 34. D A = (Ld’.A + Ld.D Ain ) Ld’Ct D B = (Ld’.B + Ld.DBin) Ld’.Ct.A D C = (Ld’.C + Ld.D Cin ) Ld’.Ct.B.A + + +

CS-352Ahmed Ezzat 39 Counters for Other Sequences (1) In some cases, sequence of counter states is not in straight binary order. Goal is to design a counter that implements a given state graph and state table using T f/fs. We should be able to derive T A, T B, T C from this table. State GraphState Table is filled from the state graph

CS-352Ahmed Ezzat 40 Counters for Other Sequences (2) First, we fill C +, B +, A + in the State table from the state graph. We can derive T C, T B, T A as before (page 33, 35); instead we will plot the next-state maps showing C +, B +, A + as function of C, B, A. Then we derive T C, T B, T A from these maps. To get the maps of T inputs from the above next-state maps: – If Q represents the present state of any f/f (C, B, A), and Q+ represents the next state (C +, B +, A + ) of the same f/f. – T input must be 1 whenever change of state is required, i.e., T =1 whenever Q+ is not equal to Q. Next state map

CS-352Ahmed Ezzat 41 Counters for Other Sequences (3) To get the maps of T inputs from the next-state maps: – If Q represents the present state of any f/f (C, B, A), and Q+ represents the next state (C +, B +, A + ) of the same f/f. – T input must be 1 whenever change of state is required, i.e., T =1 whenever Q+ is not equal to Q.

CS-352Ahmed Ezzat 42 Counters for Other Sequences (4) To form T Q map, we simply put 1 in each square of the T Q map for which Q + is different from Q. Derivation of T inputs from the next-state map

CS-352Ahmed Ezzat 43 Counters for Other Sequences (5) Counter implementation using T f/fs and Gates

CS-352Ahmed Ezzat 44 Counters for Other Sequences (6) Counter Design Using D Flip-Flops For a D f/f, Q + = D, so the D input is identical with the next-state map. Equations for D are equal to those derived from the Q + map. The following equations can be read directly from the next-state map (page 40). D C = C + = B’ D B = B + = C + BA’ D A = A + = CA’ + BA’ = A’(C + B)

CS-352Ahmed Ezzat 45 Counters for Other Sequences (7) Counter Design Using D Flip-Flops Counter implementation using D f/fs:

CS-352Ahmed Ezzat 46 Counter Design Using S-R and J-K Flip-Flops (1) We would like to develop a procedure to derive S-R f/f input equations similar to what we did with T and D f/fs. Procedure to design S-R f/f (derive input equations) is similar to what we have done with binary counters. (a) Standard Truth Table (b) Re-organize the Truth Table to be Q, Q’ base (c) Same as (b) with adding X as don’t care

CS-352Ahmed Ezzat 47 Counter Design Using S-R and J-K Flip-Flops (2) Next, we will redesign counter (page 39) using S-R f/f. State table of (page 39) is repeated here with columns added for S, R inputs. These new columns are filled from the (c) table in (page 46).

CS-352Ahmed Ezzat 48 Counter Design Using S-R and J-K Flip-Flops (3) We will derive S-R input maps (equations) from the next-state (Q + ) maps rather than from the state table: Next-State Map S-R F/F Map & Equations

CS-352Ahmed Ezzat 49 Counter Design Using S-R and J-K Flip-Flops (4) Resulting S-R f/f Circuit:

CS-352Ahmed Ezzat 50 Counter Design Using S-R and J-K Flip-Flops (5) Design of J-K f/f is similar to S-R f/f, except that J=K=1 is allowed (f/f change state)  (page 46): (a) Standard Truth Table (b) Re-organize the Truth Table to be Q, Q’ base (c) Same as (b) with adding X as don’t care

CS-352Ahmed Ezzat 51 Counter Design Using S-R and J-K Flip-Flops (6) Next, we will redesign counter (page 39) using J-K f/f. State table of (page 39) is repeated here with columns added for J, K inputs. These new columns are filled from the (c) table in (page 50).

CS-352Ahmed Ezzat 52 Counter Design Using S-R and J-K Flip-Flops (7) We will derive J-K input maps (equations) from the next-state (Q + ) maps rather than from the state table: Next-State Map S-R F/F Map & Equations

CS-352Ahmed Ezzat 53 Counter Design Using S-R and J-K Flip-Flops (8) Resulting J-K f/f Circuit: Logic J-K circuit (omitting the feedback lines)

CS-352Ahmed Ezzat 54