10Gb/s Inverter Based Cascode Transimpedance Amplifier in 40nm CMOS Technology M. Atef, Hong Chen, and H. Zimmermann Vienna University of Technology Institute of Electrodynamics, Microwave and Circuit Engineering

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

CMOS Optical Receivers CMOS silicon integrated circuits appear to be the best technology that can achieve the required level of integration with reasonable speed, cost, and yield. As CMOS technology is downscaled, the peak transit frequency of the transistors is increased. However, the supply voltage of nanometer CMOS chips must be decreased to prevent destructive breakdown in the MOSFETs and to save power in digital circuits. Another drawback that the threshold voltage is lowered by a smaller ratio than the power supply voltage which limits the circuits cascading to increase the total gain and obtaining the maximum speed. Also, the transistor output resistance decreased with down scaling the transistors, as a result the intrinsic voltage gain of a transistor will be smaller.

CMOS Optical Receivers Therefore, more than one stage is needed for high-gain high-speed amplifiers, which increase the overall power consumption and may affect the amplifier stability. The inverter structure shows a better noise behavior than a simple common- source amplifier (CS) because of its higher transconductance. Unfortunately, large parasitic capacitance is also associated with large devices. The gate–source capacitances of the devices add directly to the input capacitance. Also the gate–drain capacitance appears directly across the feedback resistor and due to the Miller effect, this capacitance can be the limiting factor with regards to bandwidth and can dominate over the photodiode capacitance.

CMOS Optical Receivers A voltage-gain stage employing the cascode configuration can be used to boost the voltage-gain with no further degradation of bandwidth from the parasitic capacitance. The principle of this circuit has been known from operational amplifiers. Such a circuit has the advantage to work at low voltages and it has the advantage of a cascode stage increasing the bandwidth. Therefore, it is suitable for high-speed CMOS circuits at low supply voltages. The proposed TIA employs an inverter based cascode to achieve a higher bandwidth at lower power consumption than with the normal CS-TIA and a better sensitivity than with the conventional inverter based TIA.

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

Inverter Based Cascode TIA Fig,1 (a) Conventional inverter based TIA circuitry , (b) circuitry of the proposed Inv-Cascode-TIA, and (c) layout of the TIA with the single ended post amplifier

Inverter Based Cascode TIA The conventional inverter based TIA transimpedance gain is given by: 𝑍 𝑇,𝑖𝑛𝑣 0 ≈ 𝐴 𝑖𝑛𝑣 ∙ 𝑅 𝐹𝐵 2 𝑅 𝐹𝐵 + 𝑟 𝑑𝑠,𝑝1 // 𝑟 𝑑𝑠,𝑛1 𝐴 𝑖𝑛`𝑣 +1 (1) Where 𝐴 𝑖𝑛𝑣 =( 𝑔 𝑚,𝑛1 + 𝑔 𝑚,𝑛2 ). 𝑟 𝑑𝑠,𝑝1 //𝑟 𝑑𝑠,𝑛1 (2) 𝐵𝑊 𝑖𝑛𝑣 ≈ 1+ 𝐴 𝑖𝑛𝑣 2𝜋 𝑅 𝐹𝐵 ( 𝐶 𝑃𝐷 + 𝐶 𝑃𝐴𝐷 +𝐶 𝑔𝑠,𝑛1,𝑝1 + 𝐶 𝑔𝑑,𝑛1,𝑝1 ∙(1+ 𝐴 𝑖𝑛𝑣 )) (3) The main advantage of the inverter based TIA is its higher gain 𝐴 𝑖𝑛𝑣 compared to the TIA with CS amplifier. The inverter based cascode TIA transimpedance gain is given by: 𝑍 𝑇,𝑖𝑛𝑣𝐶 0 ≈ 𝐴 𝑖𝑛𝑣𝐶 ∙ 𝑅 𝐹𝐵 𝐴 𝑖𝑛𝑣𝐶 +1 (4) 𝐴 𝑖𝑛𝑣𝐶 = ( 𝑔 𝑚,𝑛1 + 𝑔 𝑚,𝑛2 ).( 𝑟 𝑜1 //𝑟 𝑜2 )= 𝑔 𝑚,𝑛1 + 𝑔 𝑚,𝑛2 ∙ 𝑔 𝑚,𝑛2 ∙ 𝑟 𝑑𝑠,𝑛2 ∙𝑟 𝑑𝑠,𝑛1 //(𝑔 𝑚,𝑝2 ∙ 𝑟 𝑑𝑠,𝑝2 ∙𝑟 𝑑𝑠,𝑝1 ) 𝑔 𝑚,𝑛2 ∙ 𝑟 𝑑𝑠,𝑛2 ∙𝑟 𝑑𝑠,𝑛1 //(𝑔 𝑚,𝑝2 ∙ 𝑟 𝑑𝑠,𝑝2 ∙𝑟 𝑑𝑠,𝑝1 ) (5)   𝐵𝑊 𝑖𝑛𝑣𝐶 ≈ 1+ 𝐴 𝑖𝑛𝑣𝐶 2𝜋 𝑅 𝐹𝐵 𝐶 𝑃𝐷 + 𝐶 𝑃𝐴𝐷 + 𝐶 𝑔𝑠,𝑛1,𝑝1 + 𝐶 𝑔𝑑,𝑛1 + 𝐶 𝑔𝑑,𝑝1 (6)

Inverter Based Cascode TIA Due to the high output resistance of the cascode implementation the voltage gain of the cascode structure is higher than that of the regular inverter. The transimpedance gain of the Inv-Cascode TIA 𝑍 𝑇,𝑖𝑛𝑣𝐶 , is a little bit higher than the transimpedance gain 𝑍 𝑇,𝑖𝑛𝑣 of regular inverter because of its higher voltage gain. The bandwidth of the inverter based cacode TIA BW invC in is much higher than the regular inverter BW inv introduced because of two reasons: First, the higher cascode voltage gain. The second is the Miller capacitance effect for C 𝑔𝑑 which is amplified by A ,𝑖𝑛𝑣 at the input node.

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

Post Amplifiers Fig.2: Single ended to differential converter, differential post amplifier and 50Ω output driver  

Post Amplifiers There is a need for a post amplifier and for a 50Ω driver to have enough gain and to interface to the measurement setup. The Inv-Cascode-TIA’s single-ended output is fed to a CS amplifier which makes amplification and level shifting to the input of the converter in front of the differential post amplifier (from 0.6V to 0.9V). The second input of the single- ended to differential converter is biased through a low-pass filter coming from the TIA output. The differential output stage is better than a single-ended one with respect to common mode rejection and power supply noise. The next stage after the first differential post amplifier is a pre-driver stage to increase the gain and make the interface to the 50Ω driver. The last stage in the optical receiver is a 50Ω differential output driver to make the interface between chip and the measurement setup.

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

Post Layout Simulation layout of the TIA with the single ended post amplifier Fig.3: Post layout simulated optical receiver frequency response. The TIA alone consumes 3.01mW, and the total chip power dissipation is 19.25mW. The active chip area of the complete optical receiver is 0.09mm2. The optical receiver has a bandwidth of 7GHz. The overall transimpedance gain is 69.2dBΩ. The TIA itself has a bandwidth of 8GHz and a transimpedance gain of 55.3dBΩ.

Post Layout Simulation Fig.5: Eye diagram of the optical receiver at a data rate of 10Gbit/s, PRBS 215-1 and an input current of 10µA   The average input referred noise current density is 12.3pA/√Hz and the integrated input referred noise current is 1.01µA. A sensitivity of -21.4dBm is obtained for the presented optical receiver for BER=10-12 at a data rate of 10Gbit/s. Figure 5 shows the eye diagram at 10Gbit/s with PRBS=215-1 and an input photodiode current of 10µA.

Post Layout Simulation (b) (c) Fig.4: Monte-Carlo simulation for the optical receiver (a) transimpedance gain, (b) output voltage offset and (c) bandwidth are calculated for 1000 Monte-Carlo runs. Then the mean value of the transimpedance gain, offset voltage, and bandwidth are 2.83kΩ with 475Ω standard deviation, 0.1mV with 34.5mV standard deviation, and 6.98GHz with 370 MHz standard deviation, respectively.

Post Layout Simulation Table I compares the post-layout simulated performance of the presented Inv-Cascode-TIA along with other recently published 10Gb/s TIAs in CMOS technology. The presented TIA shows superiority in terms of Figure of Merit (FoM) which is defined by :  𝐹𝑜𝑀= 𝐺𝑎𝑖𝑛 𝛺 .𝐵𝑊 𝐺𝐻𝑧 .𝐶(𝑝𝐹) 𝑃𝑜𝑤𝑒𝑟 𝐷𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛 𝑚𝑊 .𝐼𝑛𝑝𝑢𝑡 𝑁𝑜𝑖𝑠𝑒(µ𝐴)  

CMOS Optical Receivers Inverter Based Cascode TIA Outline CMOS Optical Receivers Inverter Based Cascode TIA Post Amplifiers and Output Driver Post Layout Simulation Results Conclusions

Conclusion A 10Gb/s high sensitivity transimpedance amplifier in 40nm CMOS is presented. The transimpedance amplifier achieves a transimpedance gain of 55.3dBΩ, 8GHz bandwidth with 0.45pF total input capacitance. The power consumption of the TIA is 3.01mW and the complete chip dissipates 19.25mW for a 1.2V single supply voltage. The complete optical receiver has a 69.2dBΩ transimpedance gain and 7GHz bandwidth. The optical receiver shows an optical sensitivity of –21.4dBm for a BER= 10-12. The introduced Inv-Cascode-TIA shows a high performance compared to the conventional inverter based TIAs due to the higher output resistance and reduction of the Miller capacitance at the input node By using the Inv-Cascode-TIA an optical receiver with higher bandwidth and sensitivity can be designed at low power consumption.

Thanks for your Attention ! For any questions, please contact Mohamed Atef: mohamed.abdelaal@tuwien.ac.at