CALTECH CS137 Fall2005 -- DeHon 1 CS137: Electronic Design Automation Day 2: September 28, 2005 Covering.

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Presentation transcript:

CALTECH CS137 Fall DeHon 1 CS137: Electronic Design Automation Day 2: September 28, 2005 Covering

CALTECH CS137 Fall DeHon 2 Why covering now? Nice/simple cost model problem can be solved well –somewhat clever solution general/powerful technique show off special cases –harder/easier cases show off things that make hard show off bounding

CALTECH CS137 Fall DeHon 3 Problem Implement a “gate-level” netlist in terms of some library of primitives General –easy to change technology –easy to experiment with library requirements (benefits of new cells…)

CALTECH CS137 Fall DeHon 4 Input netlist library represent both in normal form –nand gate –inverters

CALTECH CS137 Fall DeHon 5 Elements of a library - 1 INVERTER2 NAND23 NAND34 NAND45 Element/Area CostTree Representation (normal form) Example: Keutzer

CALTECH CS137 Fall DeHon 6 Elements of a library - 2 AOI21 4 AOI22 5 Element/Area Cost Tree Representation (normal form)

CALTECH CS137 Fall DeHon 7 Input Circuit Netlist ``subject DAG’’

CALTECH CS137 Fall DeHon 8 Problem statement into this library Find an ``optimal’’ (in area, delay, power) mapping of this circuit (DAG)

CALTECH CS137 Fall DeHon 9 What’s the problem? Trivial Covering subject DAG 7NAND2 (3) = 21 5INV (2) = 10 Area cost 31

CALTECH CS137 Fall DeHon 10 Cost Models

CALTECH CS137 Fall DeHon 11 Cost Model: Area Assume: Area in gates or, at least, can pick an area/gate –so proportional to gates e.g. –Standard Cell design –Standard Cell/route over cell –gate array

CALTECH CS137 Fall DeHon 12 Standard Cell Area invnand3AOI4invnor3Inv All cells uniform height Width of channel determined by routing Cell area Width of channel fairly constant?

CALTECH CS137 Fall DeHon 13 Cost Model: Delay Delay in gates –at least assignable to gates Twire << Tgate Twire ~=constant –delay exclusively/predominantly in gates Gates have Cout, Cin lump capacitance for output drive delay ~ Tgate + fanout  Cin Cwire << Cin or Cwire can lump with Cout/Tgate

CALTECH CS137 Fall DeHon 14 Cost Models Why do I show you models? –not clear there’s one “right” model –changes over time –you’re going to encounter many different kinds of problems –want you to see formulations so can critique and develop own –simple make problems tractable are surprisingly adequate –simple, at least, help bound solutions

CALTECH CS137 Fall DeHon 15 Approaches

CALTECH CS137 Fall DeHon 16 Greedy work? Greedy = pick next locally “best” choice 2346

CALTECH CS137 Fall DeHon 17 Greedy In  Out 6 4 2

CALTECH CS137 Fall DeHon 18 Greedy In  Out 8 11

CALTECH CS137 Fall DeHon 19 Greedy Out  In 6 4 2

CALTECH CS137 Fall DeHon 20 Greedy Out  In 8 11

CALTECH CS137 Fall DeHon 21 But… = 10

CALTECH CS137 Fall DeHon 22 Greedy Problem What happens in the future (elsewhere in circuit) will determine what should be done at this point in the circuit. Can’t just pick best thing for now and be done.

CALTECH CS137 Fall DeHon 23 Brute force? Pick a node (output) Consider –all possible gates which may cover that node –branch on all inputs after cover –pick least cost node

CALTECH CS137 Fall DeHon 24 Pick a Node

CALTECH CS137 Fall DeHon 25 Brute force? Pick a node (output) Consider –all possible gates which may cover that node –recurse on all inputs after cover –pick least cost node Explore all possible covers –can find optimum

CALTECH CS137 Fall DeHon 26 Analyze brute force? Time? Say P patterns, linear time to match each –(can do better…) P-way branch at each node… …exponential  O(depth P )

CALTECH CS137 Fall DeHon 27 Structure inherent in problem to exploit?

CALTECH CS137 Fall DeHon 28 Structure inherent in problem to exploit? There are only N unique nodes to cover!

CALTECH CS137 Fall DeHon 29 Structure If subtree solutions do not depend on what happens outside of its subtree –separate tree –farther up tree Should only have to look at N nodes. Time(N) = N*P*T(match) –w/ P fixed/bounded, technically linear in N –w/ cleverness work isn’t P*T(match) at every node

CALTECH CS137 Fall DeHon 30 Idea Re-iterated Work from inputs Optimal solution to subproblem is contained in optimal, global solution Find optimal cover for each node Optimal cover: –examine all gates at this node –look at cost of gate and its inputs –pick least

CALTECH CS137 Fall DeHon 31 Work front-to-back

CALTECH CS137 Fall DeHon 32 Work Example (area) library

CALTECH CS137 Fall DeHon 33 Work Example (area) library

CALTECH CS137 Fall DeHon 34 Work Example (area) library

CALTECH CS137 Fall DeHon 35 Work Example (area) library =8

CALTECH CS137 Fall DeHon 36 Work Example (area) library

CALTECH CS137 Fall DeHon 37 Work Example (area) library

CALTECH CS137 Fall DeHon 38 Work Example (area) library =5

CALTECH CS137 Fall DeHon 39 Work Example (area) library

CALTECH CS137 Fall DeHon 40 Work Example (area) library =8

CALTECH CS137 Fall DeHon 41 Work Example (area) library

CALTECH CS137 Fall DeHon 42 Work Example (area) library

CALTECH CS137 Fall DeHon 43 Work Example (area) library =13

CALTECH CS137 Fall DeHon 44 Work Example (area) library

CALTECH CS137 Fall DeHon 45 Work Example (area) library =15

CALTECH CS137 Fall DeHon 46 Work Example (area) library =9

CALTECH CS137 Fall DeHon 47 Work Example (area) library

CALTECH CS137 Fall DeHon 48 Work Example (area) library =16

CALTECH CS137 Fall DeHon 49 Work Example (area) library =18

CALTECH CS137 Fall DeHon 50 Work Example (area) library

CALTECH CS137 Fall DeHon 51 Work Example (area) library =18

CALTECH CS137 Fall DeHon 52 Work Example (area) library =22

CALTECH CS137 Fall DeHon 53 Work Example (area) library

CALTECH CS137 Fall DeHon 54 Work Example (area) library =21

CALTECH CS137 Fall DeHon 55 Work Example (area) library =17

CALTECH CS137 Fall DeHon 56 Work Example (area) library =19

CALTECH CS137 Fall DeHon 57 Work Example (area) library

CALTECH CS137 Fall DeHon 58 Optimal Cover library

CALTECH CS137 Fall DeHon 59 Optimal Cover library Much better than 31!

CALTECH CS137 Fall DeHon 60 Note There are nodes we cover which will not appear in final solution.

CALTECH CS137 Fall DeHon 61 “Unused” Nodes library

CALTECH CS137 Fall DeHon 62 Dynamic Programming Solution Solution described is general instance of dynamic programming Require: –optimal solution to subproblems is optimal solution to whole problem –(all optimal solutions equally good) –divide-and-conquer gets same (finite/small) number of subproblems Same technique used for instruction selection

CALTECH CS137 Fall DeHon 63 Delay Similar –Cost(node) = Delay(gate)+Max(Delay(input))

CALTECH CS137 Fall DeHon 64 DAG DAG = Directed Acyclic Graph –Distinguish from tree (tree  DAG) –Distinguish from cyclic Graph –DAG  Directed Graph (digraph) treeDAG Digraph

CALTECH CS137 Fall DeHon 65 Trees vs. DAGs Optimal for trees –why? Area Delay

CALTECH CS137 Fall DeHon 66 Not optimal for DAGs Why?

CALTECH CS137 Fall DeHon 67 Not optimal for DAGs Why? 1+1+1=3

CALTECH CS137 Fall DeHon 68 Not optimal for DAGs Why? 1+1+1= =7 ?

CALTECH CS137 Fall DeHon 69 Not Optimal for DAGs (area) Cost(N) = Cost(gate) +  Cost(input nodes) think of sets cost is magnitude of set union Problem: minimum cost (magnitude) solution isn’t necessarily the best pick –get interaction between subproblems –subproblem optimum not global...

CALTECH CS137 Fall DeHon 70 Not Optimal for DAGs Delay: –in fanout model, depends on problem you haven’t already solved (delay of node depends on number of uses)

CALTECH CS137 Fall DeHon 71 What do people do? Cut DAGs at fanout nodes optimally solve resulting trees Area –guarantees covered once get accurate costs in covering trees, made “premature” assignment of nodes to trees Delay –know where fanout is

CALTECH CS137 Fall DeHon 72 Bounding Tree solution give bounds (esp. for delay) –single path, optimal covering for delay –(also make tree by replicating nodes at fanout points) no fanout cost give bounds –know you can’t do better delay bounds useful, too –know what you’re giving up for area –when delay matters

CALTECH CS137 Fall DeHon 73 (Multiple Objectives?) Like to say, get delay, then area –won’t get minimum area for that delay –algorithm only keep best delay –…but best delay on off critical path piece not matter …could have accepted more delay there –don’t know if on critical path while building subtree –(iterate, keep multiple solutions)

CALTECH CS137 Fall DeHon 74 Many more details... Implement well Combine criteria –(touch on some later) …see literature –(put some refs on web)

CALTECH CS137 Fall DeHon 75 Big Ideas simple cost models problem formulation identifying structure in the problem special structure characteristics that make problems hard bounding solutions