School of Microelectronic Engineering EMT362: Microelectronic Fabrication Contact Technology For The VLSI Process Ramzan Mat Ayub School of Microelectronic Engineering

Lecture Objectives Able to identify ALL back-end process modules from wafer cross section. Understand the important of ohmic contact and able to describe step by step ohmic contact formation. Understand the importance of contact resistance monitoring, extraction method and test structure. Understand the application of diffusion barrier layer Able to describe silicide and salicide processes.

School of Microelectronic Engineering Main Process Modules (CMOS 1P2M 3.3V) 1. Wells Formation 2.Active Area Definition 3.Device Isolation (LOCOS) 4.Vt Adjust 5.Polygate Definition 6.Source & Drain Formation 7.Pre Metal Dielectrics Deposition (PMD) 8.Contact Definition 9.Metal-1 Deposition & Patterning 10.Inter-Metal Dielectrics Deposition (IMD) 11.Via Definition 12.Metal-2 Deposition & Patterning 13.Passivation 14.Pad Definition Full integration may require process steps FRONT END PROCESS (creating an electrically isolated devices) BACK END PROCESS (connecting the devices to form the desired circuit function.) Standard CMOS Process Flow

School of Microelectronic Engineering Back-end Process Overview

School of Microelectronic Engineering Standard CMOS Process Flow 0. Wafer Start p+ silicon substrate P-Epi 5.5 um SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 1. Pad oxidation 1 p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 2. Nitride-1 deposition p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm Nitride SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 3. Lithography N-Well/LOCOS-1 p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm Nitride Resist Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering 4. Nitride-1 Etch p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm Resist Nitride SequenceOperationEquipmentSpecification Process Control Purpose

School of Microelectronic Engineering 5. N-Well Ion Implantation p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm Phosphorus 150 keV Phosphorus Implant Resist Nitride SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 6. Resist Removal p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm Nitride remaining oxide thickness 15 ± 5 nm Phosphorus Implant SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 7. Oxidation p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm LOCOS-1 Nitride SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 8. Nitride Etch p+ silicon substrate P-Epi 5.5 um pad oxide 28 nm LOCOS-1 N-Well SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 9. P-Well Ion Implantation Boron 50 keV p+ silicon substrate Boron Implant LOCOS-1 N-Well SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 10. Well Drive-in p+ silicon substrate P-Well Pad oxide LOCOS-1 N-Well SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 11. Oxide Etch p+ silicon substrate P-Well N-Well SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 12. Pad Oxidation-2 p+ silicon substrate P-Well N-Well Pad Oxide SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 13. Nitride Deposition-2 p+ silicon substrate P-Well N-Well Pad Oxide Nitride SequenceOperation Equipment Specification Process ControlPurpose

School of Microelectronic Engineering 14. Lithography Active Area/LOCOS-2 p+ silicon substrate P-Well N-Well Resist Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering p+ silicon substrate P-Well N-Well 20. Field Oxidation Thin layer of oxide growned on nitride FOX SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 21. Oxide Etch p+ silicon substrate P-Well N-Well FOX SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 22. Nitride Etch p+ silicon substrate P-Well N-Well FOX SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 23. Oxide Etch p+ silicon substrate P-Well N-Well FOX SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 24. Sacrificial Oxide p+ silicon substrate P-Well N-Well FOX SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 25. Lithography Capacitor (Scribe-line and Test Insert) N-Well P-Well N-Well FOX Resist Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 26. Capacitor Implant (Scibe-line and Test Insert) Arsenic 150 keV Arsenic ImplantN-Well P-Well N-Well FOX Resist Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 27. Resist Removal Arsenic ImplantN-Well P-Well N-Well FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 28. Anneal Arsenic ImplantN-Well P-Well N-Well FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 28. Lithography NMOS Vth Resist Arsenic ImplantN-Well P-Well N-Well FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering 29. NMOS-Vth Implant Resist Arsenic ImplantN-Well P-Well N-Well FOX Boron 25 keV Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 30. Resist Removal Arsenic ImplantN-Well P-Well N-Well FOX Boron Implant Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 31. Anneal Arsenic ImplantN-Well P-Well N-Well FOX Boron Implant Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 32. Lithography PMOS-Vth N-Well P-Well Resist N-Well Arsenic Implant Boron Implant FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering 33. PMOS-Vth Implant N-Well P-Well Resist N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust Boron 25 keV FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 34. Resist Removal N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 35. Oxide Etch N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 36. Gate Oxidation N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 37. Polysilicon Deposition Polysilicon N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 38. Resist Coat, Backside Etch, Resist Removal Polysilicon N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 39. POCL3 Dope N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust Phosphorus Doped Polysilicon FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 40. Lithography Gate Poly N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust Resist FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering 41. Polysilicon Etch Resist N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 42. HF Dip / Resist Removal N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust Polysilicon FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 43. Oxidation N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 44. Lithography N-Channel LDD Resist N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process Control Purpose

School of Microelectronic Engineering 45. N-Channel LDD Implant Phosphorus 60 keV Resist N-Well P-Well N-Well Arsenic Implant Boron Implant Vth Adjust Boron Implant Vth Adjust FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 46. Resist Removal N-WellP-Well N-Well Arsenic Implant Boron Implant Vth Adjust LDD Capacitor FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 47. Plasma Oxide Deposition SequenceOperationEquipmentSpecification Process ControlPurpose 250 nm Plasma Oxide N-WellP-Well N-Well Arsenic Implant Boron Implant Vth Adjust LDD FOX Test Insert and Scribe-line

School of Microelectronic Engineering 48. Spacer Etch SequenceOperationEquipmentSpecification Process ControlPurpose FOX Spacer N-WellP-Well N-Well Arsenic Implant Capacitor LDD FOX Test Insert and Scribe-line

School of Microelectronic Engineering 49. Oxidation nm Oxide on Poly-Si20 nm Oxide on Substrate FOX N-WellP-Well N-Well Arsenic Implant Capacitor LDD FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 50. Lithography NMOS-S/D Resist FOX N-WellP-Well N-Well Arsenic Implant Capacitor LDD FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process ControlPurpose Anneal800 C, 15 ‘, N2ASM SB/T1To prepare wafer surface for better priming

School of Microelectronic Engineering 51. NMOS S/D Implant Arsenic 80 keV Resist FOX N-Well Arsenic Implant Capacitor LDD As+ S/D Implant P-Well FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 52. Resist Removal FOX N-Well Arsenic Implant Capacitor LDD As+ S/D Implant P-Well NMOS FOX Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 53. Anneal SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant Capacitor LDD As+ S/D Implant P-Well NMOS FOX Test Insert and Scribe-line

School of Microelectronic Engineering 54. Lithography PMOS S/D Implant FOX N-Well Arsenic Implant Capacitor LDD As+ S/D Implant P-Well NMOS FOX Test Insert and Scribe-line Sequence Operation Equipment Specification Process ControlPurpose Anneal800 C, 15 ‘, N2ASM SB/T1To prepare wafer surface for better priming

School of Microelectronic Engineering 55. PMOS S/D Implant FOX N-Well Arsenic Implant Capacitor LDD As+ S/D Implant P-Well NMOS BF2 Implant PMOS FOX BF2 S/D Implant Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 56. Resist Removal FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 57. BPSG Deposition : To isolate metal 1 from polysilicon lines and gates SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Test Insert and Scribe-line

School of Microelectronic Engineering 58. Reflow FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 59. Lithography Contact FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Resist Test Insert and Scribe-line Sequence Operation Equipment Specification Process ControlPurpose Anneal800 C, 15 ‘, N2ASM SB/T1To prepare wafer surface for better priming

School of Microelectronic Engineering 60. Contact Etch FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Resist SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 61. Resist Coat, Backside Etch, Resist Removal FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Resist Test Insert and Scribe-line SequenceOperation Equipment Specification Process ControlPurpose

School of Microelectronic Engineering 62. Titanium/Titanium Nitride Deposition SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Ti/TiN Test Insert and Scribe-line

School of Microelectronic Engineering 63. Anneal FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG Ti/TiN Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 64. Metal 1 Deposition SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu TiN ARC Layer Test Insert and Scribe-line

School of Microelectronic Engineering 65. Lithography Metal-1 FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu TiN ARC Layer Resist Test Insert and Scribe-line Sequence OperationEquipmentSpecificationProcess ControlPurpose

School of Microelectronic Engineering 66. Metal-1 Etch/Resist Removal FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu TiN ARC Layer SequenceOperationEquipment Specification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 66. Metal-1 Etch / Capacitor FOX Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BPSG N-Well Metal 1 SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 67. Solvent Strip FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 68. Parameter Test 1 SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Test Insert and Scribe-line

School of Microelectronic Engineering 69. IMD-1 and Planarisation FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 70. Lithography Via-Contact FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Test Insert and Scribe-line Sequence OperationEquipmentSpecificationProcess ControlPurpose

School of Microelectronic Engineering 71. Via-Contact Etch FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation SequenceOperationEquipmentSpecification Process Control Purpose Test Insert and Scribe-line

School of Microelectronic Engineering 72. Resist Removal FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation SequenceOperationEquipmentSpecification Process Control Purpose Test Insert and Scribe-line

School of Microelectronic Engineering 73. Metal 2 Deposition AlSiCu TiN ARC-Layer FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 74. Lithograpy Metal 2 AlSiCu FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Test Insert and Scribe-line Sequence OperationEquipmentSpecificationProcess ControlPurpose

School of Microelectronic Engineering 75. Metal 2 Etch / Resist Removal Metal 2 FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation SequenceOperationEquipmentSpecification Process ControlPurpose Test Insert and Scribe-line

School of Microelectronic Engineering 76. Solvent Strip Metal 2 FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Test Insert and Scribe-line SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 77. Passivation SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Metal 2 Passivation P+ Substrate Test Insert and Scribe-line

School of Microelectronic Engineering 78. Lithography Bond Pads Field Oxide BPSG Metal 1 Metal 2 Planarisation Passivation Resist Sequence OperationEquipmentSpecificationProcess ControlPurpose

School of Microelectronic Engineering 79. Passivation Etch Resist Silicon Substrate Field Oxide BPSG Metal 1 Metal 2 Planarisation Passivation Resist Bond Pad opening SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 80. Resist Removal / Solvent Strip Resist Silicon Substrate Field Oxide BPSG Metal 1 Metal 2 Planarisation Passivation Bond Pad opening SequenceOperationEquipmentSpecification Process ControlPurpose

School of Microelectronic Engineering 81. Anneal SequenceOperationEquipmentSpecification Process ControlPurpose Resist Silicon Substrate Field Oxide BPSG Metal 1 Metal 2 Planarisation Passivation Bond Pad opening

School of Microelectronic Engineering 82. PATMOS / Final Test SequenceOperationEquipmentSpecification Process ControlPurpose FOX N-Well Arsenic Implant LDD As+ S/D Implant P-Well NMOSPMOS Capacitor FOX BF2 S/D Implant BPSG AlSiCu Planarisation Metal 2 Passivation P+ Substrate Spacer Test Insert and Scribe-line

School of Microelectronic Engineering Dielectric Thin Film Process Review

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Two Types of Thin Film School of Microelectronic Engineering  Dielectric Film (CVD Process)  Conducting Film (PVD Process)

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Dielectric Thin Film Applications School of Microelectronic Engineering  Front-End-Of-Line (FEOL)  Shallow Trench Isolation (STI)  Sidewall Spacer  Back-End-Of-Line (BEOL)  Pre-Metal Dielectric (PMD)  Inter Metal Dielectric (IMD)  Passivation

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Shallow Trench Isolation (STI)

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Sidewall Spacer

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Pre-Metal Dielectric USG BPSG

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Inter Metal Dielectric TEOS - O3 oxide (4000A) SOG (1500A) TEOS-02 (4000A)

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Inter Metal Dielectric

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Passivation

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Dielectric Thin Film Applications – The Challenges School of Microelectronic Engineering  Planarization of Interlevel Dielectric  Low-k dielectric materials  Filling of high aspect ratio contact holes and vias  Dielectrics / conductors material integration

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Dielectric Thin Film Applications – The Requirements School of Microelectronic Engineering  Low-k  High breakdown  Less moisture absorption  Good adhesion to aluminum  Stable at temperature of up to 500 º C  Good conformality  Good thickness uniformity  Easily etched

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Dielectric Thin Film – Basic Characteristics School of Microelectronic Engineering  Step Coverage & Conformality  Gap Fill Capability

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Step Coverage School of Microelectronic Engineering  Step coverage is the measurement of the deposited film reproducing the slope of a step on the substrate surface.  Aspect Ratio = h / w  Conformity = b / c  Sidewall Step Coverage = b / a  Bottom Step Coverage = d / a

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 School of Microelectronic Engineering  Factors affecting step coverage.  arriving angle of the precursors  precursors surface mobility

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 The Effect of Arriving Angle School of Microelectronic Engineering  The larger the arriving angle, more precursor molecules will be adsorbed.  For the precursor with low surface mobility, a thicker film will be deposited at that area.  Can cause undesirable effects such as overhang and void.

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 The Control of Arriving Angle School of Microelectronic Engineering  Reducing process pressure, longer MFP, better step coverage  Tapering opening

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 The Effect Surface Mobility School of Microelectronic Engineering  Surface mobility depends on precursor chemistry and substrate temperature.  Comparison of APCVD and LPCVD films conformality

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Gap Fill Capability School of Microelectronic Engineering  To fill the gap without creating void is very important.  Void can cause defect and reliability problem

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Surface Mobility School of Microelectronic Engineering  The ability of the precursors to migrate on the surface. Very important characteristics for good step coverage and gap- fill capability.

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Surface Adsorption School of Microelectronic Engineering  Adsorption is a process that occurs when a gas or liquid accumulates on the surface od a solid, forming a molecular or atomic film.  Chemisorption  Physisorption

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Chemisorption School of Microelectronic Engineering  Chemical bond is formed between an atom in the surface and an atom in the adsorbed precursor molecule.  The adsorbed atoms/molecules are held to the surface with energy usually exceeding 2 eV.  The chemisorbed precursors have very low surface mocility

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Physisorption School of Microelectronic Engineering  Adsorbed molecules are held to the surface with forces much weaker than with chemisorption, normally < 0.5 eV  High surface mobility, thermal energy at 400 º C and ion bombardment are able to provide enough energy to cause physisorbed precursors to breakfree and leave the surface.

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 Sticking Coefficient School of Microelectronic Engineering  The sticking coefficient is the probability that an atom or a molecule will form a chemical bond with surface atoms and chemisorb on the substrate surface in one collision with the surface.  The lower the sticking coefficient, the higher the surface mobility.

School of Microelectronic Engineering KUKUM – SHRDC INSEP Training Program 2006 CVD Precursors School of Microelectronic Engineering  Silane, SiH 4  TEOS (tetra-ethyl-oxy-silane), Si(OC 2 H 5 ) 4

School of Microelectronic Engineering POLYCIDE – POLYSILICON GATE + TUNGSTEN SILICIDE (WSix)

School of Microelectronic Engineering CONTACT – FILLED WITH TUNGSTEN (CALLED TUNGSTEN PLUG)

School of Microelectronic Engineering

PMD – PRE METAL DIELECTRICS (USG + BPSG) PMD

School of Microelectronic Engineering PMD USG BPSG

School of Microelectronic Engineering METAL-1- CONSISTS OF BARRIER, INTERCONNECT AND ARC

School of Microelectronic Engineering ILD- INTER LAYER DIELECTRIC (NITRIDE / SILANE OXIDE, TEOS 03 OXIDE, SOG, TEOS O2 OXIDE) ILD

School of Microelectronic Engineering METAL-2

School of Microelectronic Engineering PASSIVATION

School of Microelectronic Engineering  WHEN ICs ARE FABRICATED, ISOLATED ACTIVE-DEVICE REGIONS ARE CREATED WITHIN THE SINGLE-CRYSTAL SUBSTRATE.  THE TECHNOLOGY USED TO CONNECT THESE ISOLATED DEVICES THROUGH SPECIFIC ELECTRICAL PATHS EMPLOYS HIGH-CONDUCTIVITY, THIN FILM CONDUCTOR MATERIALS FABRICATED ABOVE THE SIO2 INSULATOR THAT COVERS THE SILICON SURFACE.  WHEREVER A CONNECTION IS NEEDED BETWEEN A CONDUCTOR FILM AND THE SILICON SUBSTRATE, AN OPENING IN THE SIO2 MUST BE PROVIDED TO ALLOW SUCH CONTACT TO OCCUR. THE NEED FOR CONTACT

School of Microelectronic Engineering GATE Xj  In MOSFET, current enters the contact perpendicular to the wafer surface, then travels parallel to the surface to reach channel.  The parasitic series resistance, R S of the current path from the contact to the edge of the channel can be modeled as; R S = R co + R sh + R sp + R ac R ac R sp R sh R co PMD METAL

School of Microelectronic Engineering Where; Rco – contact resistance between the metal and the S/D region Rsh – sheet resistance of S/D regions Rsp – resistance due to current crowding effect near the channel end of the source Rac – accumulation layer resistance Rco need to be accurately determined !

School of Microelectronic Engineering THEORY OF METAL-SEMICONDUCTOR CONTACT V I V V I I Ideal ohmic contact Rectifying contact Low-resistance ohmic contact  Ideal non-rectifying contacts would exhibit no resistance to the flow of current in both directions.  In general, metal-semiconductor contacts tend to exhibit non-ohmic I-V (due to the work-function different of metal and semiconductor, potential energy barrier exist between metal-semiconductor at thermal equilibrium). For e.g. Metal-n type S/C potential barrier is 0.5V.

School of Microelectronic Engineering EvEv EcEc EFEF EFEF vacuum level qΦmqΦm metal n-type s/conductor qΦsqΦs EcEc e e e e Energy band diagram of metal-semiconductor contact potential barrier EFEF Rectifying contact

School of Microelectronic Engineering  However, it is still possible to fabricate metal - s/c contacts with I-V characteristics that approach those of ideal case. This actual contact is referred as low-resistance ohmic contact.  Surface concentration in silicon is high, N D > cm -3  Contact sintering (furnace anneal ~450ºC after metal deposition)

School of Microelectronic Engineering SPECIFIC CONTACT RESISTIVITY, ρ c  PHYSICAL PARAMETERS THAT CHARACTERIZE THE INTERFACE RESISTIVITY OF METAL – S/C CONTACT.  THE ρ c DESCRIBES THE INCREMENTAL RESISTANCE OF AN INFINITELY SMALL AREA OF INTERFACE I.E THE INTERFACE QUALITY.  UNIT  -cm 2

School of Microelectronic Engineering SPECIFIC CONTACT RESISTIVITY, ρ c EXTRACTION GATE A – area of contact interface V Assume the current density over the entire area A is uniform; ρ c = R k / A Where R k is V/I

School of Microelectronic Engineering SPECIFIC CONTACT RESISTIVITY, ρ c EXTRACTION  Three most commonly used structures  Cross-bridge Kelvin Resistor – CBKR  Contact-end resistor – CER  Transmission line tap resistor - TLTR In all of these structures,  a specific current is sourced from the diffusion level up to metal level through the contact window.  a voltage is measured between the two levels using two other terminals.

School of Microelectronic Engineering metal diffusion L L I CROSS-BRIDGE KELVIN RESISTOR ℓ δ

School of Microelectronic Engineering PROCEDURE FOR EXTRACTING ρ c FROM CBKR ℓ δ 1.2 sets of CBKR test structures of varying contact sizes, ℓ varying in length between 1 to 25 um, with at least 2 different δ for each set of test structures. 2.The diffused region under the contacts for CBKR should be fabricated to closely emulate the actual junctions to be built in the actual devices. Normally both contacts on p+ and n+ need to be built. The sheet resistance( ρ sh ) of diffused layers is to be measured. 3.After test structures have been fabricated, the value of Kelvin contact resistance, R k = V/I, of each contact is measured. 4.The value of log 10 (R k / ρ sh ) is calculated for each contact. 5.The value of log 10 (ℓ/δ ) is calculated for each contact. 6.The values of log 10 (R k / ρ sh ) versus log 10 (ℓ/δ ) are plotted for every set of different δ 7.Two value of y = ℓ t / δ could be extracted from the curves where ℓ t is the transfer length and defined as ℓ t = √ ρ c /ρ sh (ℓ t is effective length of current crowding effect) 8.Since the δ values are known, ℓ t can be found from ℓ t = y δ 9.Since ℓ t = √ ρ c /ρ sh, ρ c is found from ρ c = ℓ t 2 ρ sh

School of Microelectronic Engineering SPECIFIC CONTACT RESISTIVITIES OF VARIOUS METAL-SI CONTACTS METAL-SI ρ c (  -  m 2 ) AlSi to n+ Si 15 AlSi-TiN to n+ Si 1.0 AlSi-TiN to p+ Si 20 CVD W to n+ Si 11 Al-Ti:W – TiSi2 to p+ Si Al-Ti:W – TiSi2 to n+ Si 13-25

School of Microelectronic Engineering CONTACT CHAIN FOR R CO MONITORING  Generally, accurate value of Rco cannot be extracted from resistance data obtained from simple contact chain structure.  However, these kinds of contact chains are useful to provide rapid monitoring of the contact-fabrication process.

School of Microelectronic Engineering contact metal diffused region PMD PAD 1 PAD 2 P-substrate n+ R 12 = V 12 / I 12 R co = R 12 / number of contact

School of Microelectronic Engineering BASIC PROCESS SEQUENCE OF CONVENTIONAL OHMIC-CONTACT  Creation of heavily doped regions (n+ or p+)  A window is etched in the oxide (contact hole etched in PMD)  Contact pre-clean (remove particles, contaminants and native oxide)  Metal deposition  Sintering or annealing process

School of Microelectronic Engineering FORMATION OF HEAVILY DOPED REGIONS  Dopants selectively introduced through ion implantation or diffusion process  Masking layer is used to restrict the introduction of dopants into the desired regions  Heavy doping is needed, however the maximum doping concentration is limited by the solid solubility of material.  Clustering effect may reduce the electrically active dopants N D > 10 19

School of Microelectronic Engineering FORMATION OF CONTACT OPENING  Key step in the fabrication of contact structure  The minimum size of contact holes usually determined by the minimum resolution capability of patterning technology. Contact size normally the same as gate length for e.g 0.5um CMOS technology, gate length = 0.5um, contact size = 0.5um (refer to the design rules).  In older technology (>2.0um process), wet etching is used for contact etch. Wetting and by product is introduced into the oxide etchant plus the application of ultrasonic agitation.  Due to the isotrapic nature of wet etching, it is ineffective for the etching of smaller contact holes.  Dry etching of contact etch is developed. N D > 10 19

School of Microelectronic Engineering  Dry etch introduced a new set of problems;  polymer contamination – by product of dry etching.  damage of silicon surface (high energy radicals in plasma), this plasma also could damaged gate oxide (plasma damaged, antenna structure is used to monitor this effect to oxide reliability)  selectivity problem  Several approaches used;  additional step to remove polymer  combined isotropic and anisotropic dry etch  combination of dry and wet etch  many others N D > 10 19

School of Microelectronic Engineering SIDEWALL CONTOURING  To give a shape that will result in good step coverage of metal.  Several approaches used;  reflow, high temperature furnace annealing after contact etch  wet etching followed by dry etch process  PR contouring followed by dry etch  many others Sloped opening

School of Microelectronic Engineering

REMOVAL OF NATIVE OXIDE  Native oxide could result in high R co  2 – 5 Å oxide posed not problem since it can be consumed by metals during sintering  Metal must be immediately deposited after native oxide removal  Methods of removing native oxide  H 2 O:HF (100:1) dip for 1 minute, followed by rinsing and drying  Sputter etch contact in sputtering system prior to metalization  in-situ dry-etch (no commercial product available) Time (min) Thickness (Å) Native oxide growth rate on Si exposed to room air

School of Microelectronic Engineering METAL DEPOSITION AND PATTERNING  Major issue is metal step coverage in the contact holes  Metal deposition technique is important;  CVD is more capable to produce good step coverage (W plug, blanket or selective deposition)  The drawback is process complexity and increase cost per process step  Preferred deposition technique for high aspect ratio contact, > A.R of 3  PVD at elevated temperature ( C)  Hot aluminum PVD process ( C)

School of Microelectronic Engineering SINTERING THE CONTACTS  Performed to allow any interface layer that exists between the metal and silicon to be consumed by a chemical reaction.  to allow metal and silicon to come into intimate contact through inter-diffusion.  Methods;  C for 30 minutes in the presence of H 2 or forming gas (a mixture of H 2 (10%) and N 2 (90%)  RTP, laser annealing and several others.

School of Microelectronic Engineering ALUMINUM JUNCTION SPIKING  Aluminum is chosen as metal interconnect because of;  Al-Si ohmic contact could be fabricated with low R co to n+ and p+  low resistivity (2.7 Ohm-cm)  excellent compatibility with SiO 2 (good adhesion).  the drawback is low melting point (660C) and low eutectic temperature of Al/Si mixtures (577 C)  Grain boundaries of polycrystalline Aluminum provide fast diffusion path for Si at temperature > 400 C.  As a result, large quantity of Si from Al-Si interface can diffuse into the Al film  Simultaneously Al from film will move rapidly to fill the voids created by the departing Si.  If the penetration of Al is deeper than the p-n junction depth below the contact, the junction will exhibit large leakage current / electrically shorted.  This effect is referred as junction spiking.

School of Microelectronic Engineering Si Beginning of heat treatment During heat treatment

School of Microelectronic Engineering METHOD TO REDUCE JUNCTION SPIKING  Silicon is added to the Al film during deposition.  sputter depositing the film from a single target containing both Al and Si.  co-evaporation of Si and Al  Silicon diffusion into Al will not occur if added Si concentration exceeds the Si solubility at process temperature (normally 1 to 2 wt % Si is added). However, this solution is only suitable for tchnology of 3um and above due to Si precipitation, thus increasing the R co.  The introduction of Diffusion Barrier between Al and Si (typical solution to junction spiking in the sub-micron CMOS process)

School of Microelectronic Engineering DIFFUSION BARRIERS  The role of this material is to prevent the inter- diffusion of Al and Si.  A diffusion barrier used is a thin film inserted between an overlying metal and underlying semiconductor material.  Such diffusion barriers should have the following characteristics;  diffusion of Al and Si through it should be low  barrier materials should be stable in the presence of Al and Si  barrier materials should adhere well to both Al and Si  barrier materials should have low contact resistivity to Al and Si  barrier materials should have good electrical conductivity  3 types of barriers  passive barriers (chemically inert with respect to Al and Si.  sacrificial barriers (react with Al and Si)  stuffed barriers (its grain boundaries is filled with other materials to block inter diffusion of Al and Si. Diffusion barrier

School of Microelectronic Engineering DIFFUSION BARRIER MATERIALS  Titanum – tungsten (Ti:W) – Stuffed Barrier  Normally sputter-deposired from a single target.  Initially used in Bipolar technology.  Major draw-back for VLSI application is the film is quite brittle and of high stress.  Polysilicon – Sacrificial Barrier  Easily integrated into NMOS technology but not as compatible with CMOS  Titanium – Sacrificial Barrier  Good diffusion barrier to Si, has a relatively short barrier capability lifetime.  Titanium Nitride – Passive Barrier  The most compatible and successful diffusion barrier in CMOS process.  impermeable barrier to Si  high activation energy for the diffusion of other materials.  chemically and thermodynamically very stable.  the lowest electrical resistivity among transitory metals.

School of Microelectronic Engineering

THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS TRANSISTOR PERFORMANCE  Series resistance Rs is a combination of;  Rs = Rco + Rsh + Rsp + Rac GATE Xj R ac R sp R sh R co PMD METAL ℓ Contact length

School of Microelectronic Engineering THE IMPACT OF INTRINSIC SERIES RESISTANCE ON MOS TRANSISTOR PERFORMANCE  When larger design rules were used, Rs was a minor component of the total MOS resistance.  As devices got smaller, Rs grew larger due to;  shrinking contact size (Rco is dependence on contact size)  shallower source / drain regions (Rsh is dependence on source / drain depth and width)  under such conditions, Rs would degrade the device performance such as;  Idsat, transconductance, Vt  Rch = [L eff + V DS ] / [  0 C ox (V GS – V T – 0.5V DS ]  Generally accepted that Rs to be kept < 10% of Rch.  A comprehensive analysis on the Rs components is needed to find the major contributor to the Rs and ways to reduce it.

School of Microelectronic Engineering SUMMARY OF THE ANALYSIS  Rsh contribution is negligible  The value of (Rac + Rsp) is likely to dominate the value of Rs for MOS devices with the channel length of < 0.5um. Minimum value of (Rac + Rsp) are achieved by fabricating source/drain junction with as steep a doping profile as possible.  Rco can also important in degrading MOS device performance. Rco is essentially determined by;  value of specific contact resistivity, ρc  contact length, ℓ. It was shown that ℓ will need to be 1 to 4 times the channel length, L, to produce with minimum value of Rco. GATE ℓ Contact length L

School of Microelectronic Engineering The requirement on minimum ℓ meaning the new way of performing contact structure is needed for deep sub-micron process technology. WHY ???

School of Microelectronic Engineering  It is not possible to increase the contact size, ℓ, because it will defeat the purpose of device shrinkage.  Enlarge active area (to accommodate larger ℓ) will also resulted in increased parasitic junction capacitance, which further degrade the device performance 2λ x 2λ DRAIN W=4λ 5λ5λ 2λ2λ Z=2λ L=2λ n + diffusion λ 2λ2λ

School of Microelectronic Engineering ALTERNATIVE CONTACT STRUCTURES self-aligned silicides (SALICIDE)  buried-oxide MOS (BOMOS) contact  elevated source / drain  selective metal deposition

School of Microelectronic Engineering Materials for Silicide Process  Group – VIII metal silicides  PtSi (28-30  ohm-cm)  CoSi2 (16-18  ohm-cm)  NiSi2 (50  Ohm-cm)  TiSi2 (13-20  ohm-cm)  TiSi2 and CoSi2 are the most developed silicide process mainly because of;  lowest resistivities among the group members  stable at temperature ~ 850 C

School of Microelectronic Engineering Silicide Process 1.Contact etch 2.Resist strip Purpose : To reduce contact resistance, Rco between metal and silicon interface 3. Titanium deposition by sputtering technique ~ 400Å GATE n+ PMD

School of Microelectronic Engineering GATE n+ 4. TiN (barrier) deposition by sputtering technique ~ 1000 Å 5. TiSi 2 (titanium silicide) formation by RTP annealing, 30s GATE n+ PMD TiSi 2

School of Microelectronic Engineering 6. W Plug deposition ~ 6000 Å (by CVD) and etch back. GATE n+ PMD TiSi 2 7. AlSiCu deposition by sputtering ~ 3000 Å 8. TiN (ARC) deposition by sputtering ~ 1400 Å GATE n+ PMD TiSi 2

School of Microelectronic Engineering 9. Metal-1 pattern and etch GATE n+ PMD TiSi 2

School of Microelectronic Engineering SALICIDE Process 1.After S/D implant 2.Resist strip GATE n+ GATE n+ 3. Titanium deposition by sputtering technique

School of Microelectronic Engineering GATE n+ 4. TiSi 2 (titanium silicide) formation by RTP annealing, 30s GATE n+ 5. Unreacted metal is selectively etched by etchant that does not attack the silicide, SiO 2 and Si substrate TiSi 2

School of Microelectronic Engineering GATE n+ 6. PMD Deposition and reflow GATE n+ 7. Contact pattern and etch Then to be deposited with TiN (barrier), W plug, AlSiCu and TiN (ARC).

School of Microelectronic Engineering Advantages of SALICIDE over conventional contact  The value of Rsh becomes negligible, ρsh silicide = 1-2 Ohm/sq versus diffused junction = ohm/sq  Rs = Rco + Rsh + Rsp + Rac  Contact area of silicide and the Si is much larger, thus, lower Rco for the same ρc