Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 1 ADC & Uniboard in Nançay - Part1 : Nancay ADC chip : 3GS/s Flash ADC in Bipolar 0.25 μm - Part2 : Uniboard digital front end (Daughter_Uni) G. Kenfack, R. Weber, C. Dumez-Viou

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 2  Goals: - Acquire the whole frequency band between 300 MHz and 1.5 GHz (UHF-L band) using only one receiver. This is the mid-frequency band of SKA. - Architecture : 6 bits (for cleaner RFI site) - RF Bandwidth : [0.1Ghz-1.5 GHz] - Price: affordable technology.  Parameters: - INL & DNL < 0.5 LSB - SFDR > 40 dB - SNR > 33 dB - ENOB > 5 bits Part1 : Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm Team : B. Da Silva, S. Bosse, S. Barth

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 3 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Architecture The flash ADC is composed of the following stages: a track and hold (T/H), comparators, a bubble correction, a Wallace Tree encoder, and a scrambler (serialiser). T&H Comp Bubble Corr & Wallace Tree Test + scrambling interface WTE

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 4 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC clock frequency of 3 GHz, it is necessary to use a T/H to perform a good rate of conversion from continuous-time to discrete-time. The T/H study is based on the architecture enclosed. The goal is to reduce the feedthrough and the droop rate and to adapt the input and the output: three parts make up this  T/H: An input buffer, T/H (switch with a charge capacitance) and an output buffer.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 5 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Comparator The comparator uses ECL D-latches which allow a simple differential architecture. To improve the system accuracy and to achieve high speed performance we need to increase the power. A trade-off is made between power and precision. For this first prototype in bipolar, we want a very high precision to compensate the loss of performance in the layout.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 6 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Digital Circuit For a conversion speed of about 3 GS/s, we need fast gates.ECL architecture gates can exceed 6 GHz operating speed. Two types of encoders, ROM and Wallace Tree Encoder (WTE). The speed is improved by almost a factor of 2 by using the WTE. The Digital part of the ADC is composed by a bubble correction (BC) and a WTE designed with ECL gates.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 7 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC System Test Interface A test system is integrated to validate the chip: direct output data with a scrambler or simple output data stream with external demux chip added. Different modes can be selected: random code or additive scrambler (simplifies the clock recovery circuit for RX and GTX circuit located in the FPGA test board).

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 8 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm S imulation results Fin= [100MHz – 1500MHz]

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 9 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC : Power consumption (RC simulation)

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 10 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Layout

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 11 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Layout Good distribution clock and Good parasitic results  ENOB > 5 bits.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 12 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm Demux Layout 1 to 8 DEMUX with LVDS compatible IOs up to 4 Gb/s serial bitrate Bipolar 0.25 μm supply voltage HVQFN32 package

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 13 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm ADC Test bench Serial data stream ADC+Demux:with parallel data stream Two ADC test boards are developed for measurement: serial interface with 6 3GHz, and parallel interface(Demux) : MHz.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 14 Nançay ADC chip : 6-bit 3GS/s Flash ADC in Bipolar 0.25 μm Conclusion The ADC chips(20) have been received this summer. The 1st test architecture with 1 bit connectivity with the random code is in use, and the serial interface can reach 2.8GHz with the FPGA board (Virtex6/ML605). More investigation (FPGA/GTX) need to be done, especially for the Virtex6 GTX configuration in order to reach 3 GHz without code error in receiving data. The ADC sample data will be captured and tested in the next few weeks. The design of the ADC/Demux board will be completed in December. Consumption: improvement to be done for the next ADC(Nov 2011) Change technology  0.13 μm SiGeC

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 15 Flexible interfaces with 10GbE link for early design stage: proof of concept. There is a need for the European radio astronomy community to bring digitised data from the antenna to the Uniboard platform. The daughter card and its ADCs can be easily shielded (close to the antenna) in an aluminium box. Digital data through optical links are appropriate for long distances (100m-200m) between the FPA and the backend (Uniboard). Part 2 : Uniboard & digital front Nancay (Daughter_Uni)  Motivation

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 16 Board description  Daughter_uni + ADC: 2 main boards - Daughter_uni encapsulates and sends the digital data stream over 2-4 x 10GbE interface through an optical link using 1 FPGA, linked to the ADC through its FMC connectors. - ADC_FMC board with a FMC connector digitises 2-4 RF inputs close to the antenna. Each ADC outputs 8 sampling rate 1 GS/s over the FMC connector (other possibilities are available).  The FMC connectors add the flexibility to use various ADCs (important for using new high speed ADCs when available) including off the shelf ADC boards which are easily pluggable onto the Daughter_Uni FMC interface.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 17 FMC interface  FMC connectors: 400 pin locations(10x40 rows).  VITA 57.1 FMC HPC connector: 160 s/e or 80 differential user-defined signals, 20 MGTs(10RX+10TX), 2MGT clocks, 4 differential clocks, 159 ground, 15 power connections(3.3v,12v…).  Speed rating: the Samtec FMC connector system with differential signaling (user defined signals) can speed up to 9 GHz. And the GTX pinout can speed up to 16GHz.

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 18 FMC interface(HPC connector) Ex Dedicated I/O

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 19 Daughter_Uni Optical link Daughter_uni 1 FPGA(Altera/Xilinx) Quad-Dual ADCs / Gs/sec 2-4 x 10Gbe for ADC data 2-4 GB DDR for local FiFo. FMC connector(HPC) Uniboard ADC / FMC Vita57

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 20 Case Study

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 21 Conclusion & Perspective  One goal of Uniboard is to promote European Radioastronomy with technical solutions for digital processing. In particular, with its flexibility, Daughter_Uni+Uniboard offers new solutions to radio astronomers.  Application for National funding will be submitted before the end of this year especially for the Nancay Phased Array Feed development (FAN).  If funded, the pcb layout will be available to Uniboard members.  A more integrated solution for SKA[300MHz-1000MHz] with a MGT integrated within the ADC Chip and VCSEL diode for the digital output will be studied by the Nancay microelectronics team (PhD position).

Guy Kenfack Bordeaux, October 2010 ADC & Uniboard in Nancay 22 ADC & Uniboard in Nancay Thank you! G. Kenfack, R. Weber, C. Dumez-Viou, B. Da Silva, S. Bosse, S. Barth