March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Visual Status 2 Rx_mac2buf I2C Fifo 31 TDCs TDC 0 Management & Control Data Control Wishbone bus RxPacket Buffer 64KB IP/UDP Packet Buffer Stream Selector (IPMUX) Rx_buf2data RxPort 1 RxPort 2 RxPort_m Management & Config. Tx_pkt2mac Tx_data2buf TxPort 1 TxPort 2 TxPort_m Flags Rx Stream Select TxPacket Buffer 32KB Flags Tx Stream Select 31 PMTs UTC time & Clock (PPS, 125 MHz) Pause Frame ADC Management & Control Hydrophone Fifo TDC 30 Fifo Nano Beacon GPIO Debug LEDs I2C Debug RS232 Temp Compass Tilt Point to Point interconnection Xilinx Kintex-7 Start Time Slice UTC & Offset counter since Time Slice Start MEM S 2 nd CPU LM32 M M WB Crossbar (1x7) WB Crossbar (3x2) S M S M M S S M M M SS S UART S M M S S M M State Machine SPI S M Flash

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Done: ◦ LM32 + WB-Crossbar + DPRAM + UART ◦ Soft-PLL FMC layout ◦ WR without PCI-express Currently: ◦ Deterministic PHY ◦ Soft PLL (hardware + software). First goal: lock onto a 125 MHz xtal and phase shift under control of LM32 via UART To do (in order of priority): ◦ Endpoint (= MAC) <= Complex! ◦ Mini-nic <= Complex! ◦ Fabric redirector <= probably less complex ◦ PPS generator <= relatively straightforward ◦ 1-wire, SysCon <= easy? Status Listing 3

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Kintex-7 GTXE2_CHANNEL RXCDRLOCK_OUT does not lock Initial Kintex-7 GTXE2_CHANNEL test with hardwired loopback on TX->RX Xilinx Core Generator Bug! ◦ RXCDR_CFG => (x" FF ") ◦ (User Guide ug 476 Table 4-18; 8B/10B encoded Data (No SSC) RXOUT_DIV = 4 Rxpll_lockdet (= RXCDRLOCK_OUT)

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology CLBv2 Test Fixture proposal October 3, 2012 FPGA REAM OLT PNPNPNPN FPGA-Rx FPGA-Tx REAM Pin Plugable Test Fixture With 8 SMAs S0S1 ‘1’ ASel0 ASel1 BSel0 BSel1 Provides electrical interface to test: 1.Optical Line Terminal 2.FPGA functionality Loopback possibilities: 1.FPGA Loopback 2.OLT Loopback 3.Normal datapath via test fixture MAX9390 ? A B (High Speed) “Debug” Connector on CLBv2 The CLBv2 Specification triggered a discussion between me and Jan- Willem Schmelling about which eventually lead to this idea

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Xilinx University Donations Xilinx granted us KC705 boards (boards not received yet) At Nikhef we already bought two KC705 boards so there will be a total of four soon. We could use all four boards…: ◦ 2 boards Peter (Master Slave) deterministic phy testing. ◦ 1 board Mesfin (porting and testing WR Spartan-6 based SPEC onto Kintex-7 based KC705) ◦ 1 board Vincent (software development) 6

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology More status… Soft PLL FMC card ◦ Layout ready  Design files in pdf format can be found in svn Hardware\FMC_SoftPLL\FMC_SoftPLL_PresentatieFiles ◦ Assemblage is started ◦ Expected mid April to be ready Porting VHDL code to Kintex ◦ Phy & endpoint ongoing ◦ Generic fifo in hold  We can use Coregen fifo for kintex Directory structure svn ◦ Proposal is made for firmware wait for feedback ◦ Proposal for embbedesoftware tbd. ◦ Proposal for hardware & software tbd. 7

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology Setup mini whiterabbit network with two SPEC cards (Master Slave) ◦ Two SPEC card configured as a PCIe card on Linux PC.  PCIe is used to configure the FPGA’s and to load LM32 software.  PCIe is also used as a VUART to debug LM32.  This setup is tested and verified already. ◦ Two standalone SPEC card.  We need to modify the WR vhdl code and make one configuration file.  Enable the real UART port for debugging the LM32.  Use BMM files to combine the fpga configuration file and the LM32 software.  Generate the msc file and store to the spi flash.  Connect the two cards as Master Slave. ◦ Conclusion  PCIe in WhiteRabbite PTP core is removed and WRPC works as expected.  This is good step towards two Kintex evaluation card setup (Master Slave). 8

March 27, 2013KM3NeT, CLBv2 Meeting Peter Jansweijer Mesfin Gebyehu Nikhef Amsterdam Electronics- Technology To Do 9 Study WR-PTP parameters and the sync protocol Study which functions are implemented in soft PLL and which in LM32 Make a simulation model for debugging soft PLL from LM32 Test and verify the soft PLL on kintex + fmcsoftpll board.