1 E. Delagnes Saclay Dec 3rd 2009. FE electronics for Micromégas Trackers

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Presentation transcript:

1 E. Delagnes Saclay Dec 3rd FE electronics for Micromégas Trackers

2E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Introduction: (Micro)Electronics for Saclay. Several versions of FE cards using the Gassiplex chip from CERN => CAST…. FE of the COMPASS tracker (12K channels operating since 2000) –SFE 16 chip (ASD 16 channels) + F1-TDC. Prototype of FE-boards for the upgrade of the COMPASS tracker: –Based on the APV chip from RAL. FE of the T2K TPC (120 K channels operating since 2009) –AFTER chip (72 channels. Ampli Shaper + SCA). FE for active target TPCs (for Nuclear Physics, 4x 20K channels): –AGET chip ( 64 channels ASD +SCA). Submitted in april 2010 FE for the Micromégas CLAS12 tracker: 40 K channels

3E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Lessons from few years working with MM (tracker for MIP) Signal duration: ns depending on the gas and on the drift & multiplication gaps. Detector capacitance always larger than what specified/foreseen. For high rate operation and in practical conditions Gain limited to ~5000 because of sparks. For detectors with long strips, the MIP signal is not so large => need for a low noise electronics. Can be very sensitive to common mode noise (as for all large detectors). Operating at very low threshold can become a nightmare. Space required for spark protection networks is large (larger than chips). No success in fully integrating the protections (at least one external capa required). Most of these limitations will disappear in case of success of the R&D on “resistive” Micromégas.

4E. Delagnes CERN/ MAMA electronics meeting Apr 16 th The CLAS12 JLAB Clas12 detectors Barrel:3x2 (X,Y) cylindrical MicromégasForward: 3x2 Disks Micromégas R=110to 240 mm / L =300 to 430 mm. R=200 mm Pitch ~ 300 µm Strip length >600mm. Total of ~5 m 2 of Micromégas. Large Magnetic Field: 5T => Lorentz angle => decrease S/N No space inside the magnet : => Baseline :FE electronics moved away (>0.8m flex cables). 3 Silicon views MM barrel MM forward

5E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Requirements for the CLAS12 MM electronics (1). Use of standard (without resistive sheet) Micromegas assumed ~40 K channels Electronics moved away from detector using 0.8m Kapton cables Particle rate < 20MHz »Hit Rate=> 48 kHz/strip (considering cluster size=4) External trigger with Max Trigger Rate = 20 kHz, fixed latency =4.5µs Inefficiency due to electronics ~ 2% Ghost hits/trigger < 8/view. Noise hits rate negligible Main functionalities (not necessary performed in this order): –Collect, amplify and filter the detector signal –Discriminate pulses –Timestamp pulses –Select pulses within a L1W ( = 100ns) window around the L1 accept signal –Measure signal charge (for centre of gravity calculation) Many requirements very similar to those of COMPASS tracker

6E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Requirements for the CLAS12 Micromegas electronics (2). Channel Occupancy: –Tocc <250ns to keep occupancy < 1.2% –High order filtering (symmetrical shape). Shaping peaking time must be – Large: To avoid ballistic deficit. To Minimize noise. –Small: to limit occupancy to be Compatible with L1W=100ns From calculations and experience from COMPASS: ~100ns peaking time should be ok => Tunable between ns.

7E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Requirements for the CLAS12 Micromegas electronics (3). Dynamic Range: –600: 9-10 bit Max Signal over ENC required. - Max Charge = 10 MIP - Threshold = MIP/10 for efficiency - Threshold = 6 * Thresholds set to 6*ENC (for noise rejection). –Max range (and MIP) depends on the detector gain => Variable gain front-end: 4 ranges selectable by slow control: i.e 160, 320, 640 fC for Micromegas. ~ 40 fC range for Si detectors. Exemple: For the160fC range: => MIP = 100 Ke- => Th = 10 Ke – => ENC should be around 1500 e- rms (gives a S/N=60) Feasible with our large detectors (+ kapton cables) ?

8E. Delagnes CERN/ MAMA electronics meeting Apr 16 th What we can learn from the AFTER chip –AMS 0.35µm technology. –Designed for the TPC of T2K. –Slow Readout (incompatible with use in trackers) –But very versatile: shaping time, dynamic range are ~matching with our needs. –Front-end part could be re-used nearly as it is associated with a custom back- end. –Modifications (50ns shaping) in progress for another experiment. –Noise deeply tested: a complete parameterization has been extracted:  Ability to predict the noise in other conditions. –1Mrad radiation hardness demonstrated in another similar chip we designed using the same technology.

9E. Delagnes CERN/ MAMA electronics meeting Apr 16 th AFTER ASIC design for T2K Main features: Input Current Polarity: positive or negativeInput Current Polarity: positive or negative 72 Analog Channels72 Analog Channels 4 Gains: 120fC, 240fC, 360fC & 600fC4 Gains: 120fC, 240fC, 360fC & 600fC 16 Peaking Time values: (100ns to 2µs)16 Peaking Time values: (100ns to 2µs) 511 analog memory cells / Channel:511 analog memory cells / Channel: Fwrite: 1MHz-50MHz; Fread: 20MHz AFTER 511 cells SCAFILTER 100ns<tpeak<2us CS A 1 channel x72(76) 76 to 1 BUFFER SCA MANAGER SLOW CONTROL Serial Interface W / R Mode CK CKCK ADC TEST In Test 120fC<Cf<600fC Power SupplyReference VoltageReference Current Asic Spy Mode CSA;CR;SCAin (N°1) Power On Reset Optimized for 20-30pF detector capaOptimized for 20-30pF detector capa 12-bit dynamic range12-bit dynamic range Slow ControlSlow Control Power on resetPower on reset Test modesTest modes Spy mode on channel 1:Spy mode on channel 1: CSA, CR or filter out No zero suppress. No auto triggering. No selective readout. IEEE Trans. Nucl Sci, June 2008 AMS 0.35µm techno transistors

10E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Requirements for the CLAS12 Micromegas electronics (3). Noise: –Must be minimized to be able to operate at low gain (if necessary to reduce spark rate). –Huge Flex + detector capacitance of pF. – ENC (for very low gain operation) seems feasible even with short shaping time: From COMPASS experience. From measurements on the AFTER chip. ENC versus input capacitance for different peaking times (120 fC range, ICSA=400 µA). Measured on the AFTER chip.

11E. Delagnes CERN/ MAMA electronics meeting Apr 16 th PROPOSED SOLUTION FOR THE CLAS12 CHIP

12E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Features common to all FE solutions: Technology choices Technology choices: –Use an existing chip: there are not a lot of available tracker chip adapted to both analog readout and large detector capacitances: the APV0.25 designed for CMS could be an option (under evaluation): + nearly a perfect chip + we already use it. -APV availability -APV not designed for high detector capacitance. -Large occupation time (RC-CR shaping). –New chip: Using a well known technology (AMS CMOS 0.35µm): + very front-end part nearly already designed. -Chip size if integrates a lot of digital electronics. Using a more recent technology: + long term availability. + prepare the future for our lab. + Less power consumption +? Less noisy. -more risky and longer development.

13E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Features common to all FE Chip solutions Packaging, modularity: –For Mmegas Prefer a QFN/QFP package (no bare die). –32-64 channel/chip is the best modularity for integration on FE boards. –128 channel/chip => big chip + package difficult to handle during test. Power consumption –As we are outside the magnet, the requirements can be relaxed/ ~5 mW/ch for the FE Chip. Configuration (Slow-control) Link: –To program test modes, peaking time, ranges, etc. Test system: –Each Channel can be pulsed individually (or all together). –For test purpose and not absolute calibration. Input Protections: –Designed to reduce the size (or even the need) of the external protections.

14E. Delagnes CERN/ MAMA electronics meeting Apr 16 th possible options for the FE chip architecture were proposed ONLY DEAD TIME-”FREE” solutions (with dual-port L1 buffers) are proposed ASD + multihit TDC: -Similar to Micromegas COMPASS tracker readout. Time Stamping + analog memory: Trigerless Front-end. Selective Readout. Analog Memory L1-Buffer (APV-like): –Similar to GEM COMPASS tracker readout. –Solution selected: Better noise rejection. Minimum work for us : the only which could match with the schedule and the available manpower.

15E. Delagnes CERN/ MAMA electronics meeting Apr 16 th VFE part of the Chip: ~ same as for AFTER

16E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Analog Memory L1 buffer solution (APV-like solution) A Switched Capacitor Array is used as a circular analogue buffer: The analog signals of all the channels is continuously sampled at F s in a Switched Capacitor Array (analogue memories). When a L1-Trigger occurs it is sent to the chips with a FIXED LATENCY (T LAT ): 3-4 samples on all channels are kept (frozen) for each triggered event. They are read and multiplexed towards an external Fread. Cells are rewritten after readout or if no trigger occurs during after T LAT. Dead Time “Free” architecture: –No interruption of writing during readout of a triggered event. – several triggered events can be stored in the SCA waiting for readout. No on-chip zero suppress: all channels are read for a trigger. c0 c511 c510 ci-2 c1 c. ci ci-1 ci+1 ci+2 EventTrigger Write pointer Read Pointer Triggered cells

17E. Delagnes CERN/ MAMA electronics meeting Apr 16 th SCA: Key parameters Fs> 2/Tp (2 samples in the trailing edge) => Fs = 20 MHz for T peak =100ns SCA DEPTH = Latency + buffer + extra cells –8 µs latency => 160 cells. –10 events derandomizing buffer => 40 cells  SCA depth = cells is feasible

18E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Main advantages of this solution Charge is directly measured. Oscilloscope-like operation makes diagnostics easier. The timing can be accurately calculated from the samples: – better than 1/Fs precision: In ATLAS LARG ECAL 1ns rms timing performed with F S =40 MHz (and tp=50ns) Pile-up can be detected and even corrected. Common mode noise can be calculated and subtracted. Low frequency noise can be partially eliminated (by subtracting baseline samples). Operations are performed before zero-suppress (discrimination)

19E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Analog sampling solution (APV-like solution) Data flow for the whole MM tracker~ 1600 the ADC output. Becomes 20 MByte/s after zero suppress. Can be reduced by 3 if an online filtering on timing is performed. For: –Simple & Proven –Very robust to bad grounding & pickup (common mode node correction) –Expertise of Saclay on SCAs Against: –Need for high frequency ADC & FPGAs close to the very front- end. –Not self triggered –Need for a L1accept “fast” and synchronous. FE CHIP L1 Accept ADC Common mode Noise extract + subtraction Zero Suppress Timing Extraction + filter

20E. Delagnes CERN/ MAMA electronics meeting Apr 16 th Short term plans. VFE part with 50ns shaping is currently designed for the AGET project. No manpower in microelectronics for this project before April Before summer 2010: Submission of a small size FE chip prototype : –16 channels x 128 cells for lower prototype cost. –Test during the fall. Check the possibility to use APV: – “successful test” with new large Micromégas of COMPASS last summer, but detailed analysis of beam data are required to check the efficiency).

21E. Delagnes CERN/ MAMA electronics meeting Apr 16 th CLAS12 & ATLAS Muon Chambers. –A lot of similar requirements. –Main difference: No auto-triggering/ need to provide fast signal for L1 trigger in the case of CLAS12. –We are open to collaborations => share expertise, cost & manpower. –As the real work on the CLAS12 chip has not really started, we can still change the selected option. –But CLAS12 tracker schedule is very tight.