Actel Antifuse FPGA Information – Radiation Tests Actel Antifuse FPGA – A54SX72A 72K gates 208 pqfp package 2.5v to 5.0v I/O tolerant $62 each for tested parts Used as controller on CCM module.

Fermilab Actel Radiation Test #1 Results Tested 8 devices at Indiana University Cyclotron in September per board. 2 on each side of a board(Fit in beam spot). Each device was loaded with a 2,012 bit shift register. Tested for SEL, SEU, TID.

TEST BOARD

SEU Tests Tested by shifting in a pattern into all 2012 FF. Connected Input to Output of shift register. Clocked at 40M hz. Shift register read out every minute while exposed to beam. Checked bit flip in pattern.

SEL Test Monitored current drain of each device while in the beam. Performed at same time as SEU test. Control Box monitors current and disables power to DUT if current goes over limit.

TID test Performed at same time as SEU and SEL. TID is determined by operation of device.

Results TID > 100K Rad SEL – 0 SEU – Maximum was 63 bit flips after 549 seconds – fluence at 2E12 p /cm^2

DATA

SEU Calculations Failures in system/time = # parts in system * failures in part * 1/fluence * expected dose rate SEU in System from FPGA = 130 * 63 * 1/2E12 * 4E11 n/cm^2/10yrs SEU per day = 0.5

Notes Actel makes commercial, rad tolerant and rad hard Antifuse FPGA. Same naming scheme – add RT or RH to front of part number. $$$$$$ Commercial parts made using the same process as the Rad parts. Parts come from two foundries. No SEL from one of the Foundries. SEU mitigation(TMR) in Critical areas.

Links L_08_01/SX72S/BNL_08_01_SX72S_MEC_Damage.htmhttp://klabs.org/richcontent/fpga_content/SXA_Series/BN L_08_01/SX72S/BNL_08_01_SX72S_MEC_Damage.htm alla.pdfhttp://rd49.web.cern.ch/RD49/RD49News/pres2303/rd49d alla.pdf

Fermilab Actel Radiation Test #2 Results Tested 8 devices at Indiana University Cyclotron in October per board. 2 on each side of a board(Fit in beam spot). Each device was loaded with a 670 bit shift register implemented with TMR. Tested for SEL, SEU, TID.

Results TID > 100K Rad SEL – 0 SEU – Maximum was 0 bit flips after 549 seconds – fluence at 2E12 p /cm^2

SEU Calculations Failures in system/time = # parts in system * failures in part * 1/fluence * expected dose rate SEU in System from FPGA = 130 * 0 * 1/2E12 * 4E11 n/cm^2/10yrs SEU per day = 0.0

Notes The TMR reduced the SEU count to 0. The non TMR design for the CCM uses about 50% of the sequential cells in the 72A part. We will implement TMR in critical areas of the design.