LPNHE - Serial links for Control in 65nm CMOS technology - 65nm CMOS - Higher density, less material, less power - Enhanced radiation hardness regular layout) - Extensive existing standard cells libraries, some rad-hard (Avago…) - Inverter delay = 20ps… - 65 nm PDK received today (May 14th ) Jean-Francois Genat May 14th 2012 G.Calderini, F.Crescioli, J.F. Genat, O.LeDortz

Designs - Two steps - Non rad hard development with present available libraries - Rad hard design using CERN design kit (see below) - CERN - A. Marchioro is evaluating 65nm CMOS providers (UMC, ST, TSMC, IBM) - CERN will make a decision and provide in November a design-kit + rad- hard libraries to the community - Present design kit (Europractice) - Focus on reliability at moderate speed O(few 100MHz) - Enhanced radiation hardness regular layout) using redundancy techniques: triplication and vote, skewed clocks etc… - Use full custom and existing standard cells libraries from Europractice - Design strategy - Analog SPICE post-layout simulations whenever felt needed (SerDes)

TSMC CMOS 65nm process and libraries Analog: Mixed-signal + RF Digital: - Voltage supply: core 1.0, 1.2V - General purpose std cells 850kGate/mm2 1.8, 2.5, 3.3V I/O transistors - Very low power - MiM and MoM (metal-oxide) caps 0.8, 1V - Thick copper for inductors LM - Diodes - Poly diff, N-well resistors - Deep N-well (noise immunity) TSMC 65nm: 35 different flavours of libraries from Synopsys Radiation Hardness 65nm <100kRad TID (TNS Vol.57 n4 Aug 2010 pp )

Control serial link - Service serial link - Use simple SPI (Serial Peripheral Interface) protocol - PLL based frequency control - JTAG controller (Testability) - Very strong radiation hardness needed (sLHC requires Mrads optimized design required at the transistor level) - Error Correcting Codes sized to very low Bit Error Rates

pix addr+ data Serial Readout Ctrl logic Goal: build a library of logic blocks specialized for readout applications Std cell kit compatible – Easy to synthesize readout trees – Usable by automatic place&route programs (ie. Cadence Encounter) Optimized to minimize routing – Compact and regular designs – Less time spent on routing in0 sel0 in1 sel1 ou t sel Basic building block → std cell First implementation of the MEPHISTO binary readout architecture for strip detectors P.Fischer NIM-A (2001) Pixel address and additional data can be multiplexed using the sel signal FIFO To be integrated with INFN Milano std cell design efforts. Develop a tight collaboration and a common characterization framework. From Francesco Crescioli

Manpower at LPNHE J.F. Genat (IR) O. Le Dortz (IR) F. Crescioli (IR) (about 2 FTE in total)