Status of the SVD DAQ Koji Hara (KEK) 2012/1/16 TRG/DAQ meeting1

SVD DAQ System Overview Analog APV25 readout is through copper cable to FADCs Sparsification and hit time finding is done in FADC modules Data is passed on through FTB to COPPER readout system Concept verified in beam tests APV25 chips Front-end hybridsRad-hard voltage regulators Analog level translation, data sparsification and hit time reconstruction Unified Belle II DAQ system ~2m copper cable Junction box ~10m Thicker copper cable FADC+PROC C O P P E R Unified optical data link (>20m) Finesse Transmitter Board (FTB) /1/16 TRG/DAQ meeting

SVD Electronics - g eneral view PIXEL DAQ Giessen Box opt F E E l e c t r o n i c s TTD RJ45 #1 #81 #80 RJ45 … #2 COPPER#40 opt FRB COPPER#2 opt FRB COPPER#1 opt FRB … #1#40 FTB#80 opt FADC#80 RJ45 FTB#2 opt FADC#2 RJ45 FTB#1 opt FADC#1 RJ45 SVD electronics SVD-CONTROLLER (SVDctlr) FCRB RJ45 SVD tracker /1/16 TRG/DAQ meeting

Current Status FTB, FADC designing and prototyping are on-going. ◦ The prototypes will be ready in  Goal of 2012 work is to establish the complete readout chain using the FTB and FADC. K. Hara and A. Ishikawa (Tohoku) are starting the integration work at KEK. SNU is also willing to join. ◦ DAQ test as a whole SVD is planed in mid  The complete DAQ system must be ready before that at KEK. 2012/1/16 TRG/DAQ meeting4

Finesse Transmitter Board (FTB) Sends FADC data through optical link to ◦ COPPER ◦ Pixel system Two first prototype boards are being sent to KEK from Krakow for firmware development. 2012/1/16 TRG/DAQ meeting5

FADC Level translation on the VME board Serial output ADCs Single powerful FPGA (Altera Stratix 4 GX) GbE interface Compensation of 30m signal cable by digital Finite Impulse Response (FIR) filter in FPGA firmware Hit time reconstruction to reduce occupancy Schedule December-January: design February: layout & firmware development March: prototype production & basic firmware development April: assembly & testing /1/16 TRG/DAQ meeting REBO part FADC part

SVD DAQ Work Plan Establish FTB-Copper connection ◦ Need to integrate Belle II link to FTB at KEK Translation from virtex to spartan is necessary.  SVD  Hara, Ishikawa (Tohoku), Joo (SNU) and Wacek (Krakow) will work on that. Establish FTB-FADC Connection ◦ FTB-FADC development at Krakow EstablishAPV25-FADC-FTB-Copper chain by 2013 BPAC 2012/1/16 TRG/DAQ meeting Integrate Belle II link to FTB and Test 2 nd FTB Prototype Production FADC prototype production and test FTB-FADC connection development Establish complete DAQ chain FTB-copper system preparation at Krakow

Summary SVD DAQ concept verified in beam tests.  Developing Belle II full DAQ chain ◦ Hara and Ishikawa starting integrating work at KEK. FTB and FADC prototypes are being produced.  Firmware development will be done to establish the connection. ◦ Need to translation Belle II link to spartan6 Establish full DAQ chain by 2013 BPAC 2012/1/16 TRG/DAQ meeting8

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SVD FINESSE COPPER in Cracow Prototype - tests setup FPGA Spartan6 RJ45 OpTr DRIVERS POWER OSC 42MHz 160 pin connector ext POWER Regs handl DRIVERS Clock distrib RJ45 config FPGA Spartan6 RJ45 OpTr DRIVERS POWER OSC 42MHz 160 pin connector ext POWER Regs handl DRIVERS Clock distrib RJ45 config FTB prototype – FINESSE adapter SVD FINESSE 42 MHz Power /1/16 TRG/DAQ meeting