Detector topic: MVD October 17 MVD status: activities progress issues identified by the SG recent changes Main risks to perform installation as presented in the past October 20 FAIR schedule with MSV version Daniela Calvo on behalf of the MVD group

From SG report Summary:  The system is well under control; the performance of the main components has been confirmed in test experiments, the system has been implemented in CAD and the software in PandaRoot.  The financing of the MVD depends to 44% (2.6 M€) on Italian financing.  The full financial support must be secured before the CERN-IBM contract runs out Otherwise the detector cannot be finished by OK ? risk

Remarks from MVD side.... The financing of the MVD depends to 44% (2.6 M€) on Italian financing ‘The total requested money for the MVD is 5.9 M€. Of this 2.3 M€ are available to be spent now or secured by firm commitments (Jülich-Hessen). 2.6 M€ should come from Torino. About 1 M€ still have to be asked for. The funding profile peaks in the years 2016 – 2018’ YES! It is true for Italian part and it is an EOI, but it is the same for ~ 1.1 MEUR asked to BMBF and for other components of PANDA apparatus! Funding agengySecured amount, 2014 [kEUR]EoI [kEUR] FAIR budgetApproved GiessenBMBF JulichGSI TorinoINFN2643 Total cost: 6.26 MEUR In the table the number are in kEUR

Remarks from MVD side.... The full financial support must be secured before the CERN-IBM contract runs out. Otherwise the detector cannot be finished by The IBM foundries at East Fishkill and Burlington have been sold to Global Foundries, including the 130 nm CMOS line used for the pixel readout chip. IBM is paying 2.3b$ to GF over 3 years to keep the foundries open (till middle of 2017) This would give sufficient time to complete the engineering run and the production of the ToPix chip, in the case of a normal evolution of the FAIR/PANDA projects, following the past schedules !

...but from February 2015 Disruptive situation with negative effects on all the groups involved in the MVD project Giessen: Last semester 2015: Funding by BMBF reduced at minimum for both positions (...phd students to be graduated asap...) and R&D (Survival situation!) New year- 2016: Funding reduced at minimum for both positions and R&D. Much less than till now... the position number has been reduced and redirected to simulations for a NEW concept of PANDA (?) No funding for production. Juelich: Last semester of 2015: Delay of activities at ZEA-1 and ZEA-2 Funding situation not clear New year- 2016: The situation is not clear yet Torino: Last semester of 2015: very low priority assigned to the technical supports (electronics and mechanics) New year-2016: technical staff dedicated to MVD moved to other projects funds have been suspended, which also means that the researchers had to apply to other projects the partecipation to the MVD is based on volunteers.... a political solution at higher level (read INFN management!) could invert the direction of this situation!

Now a new schedule of MSV… Installation/commissioning

MVD Timeline evolution… ActivityStartEndStartEnd Design and planning Production/ Procurement Manufacturing of pre-series/prototype Manufacturing of series/component Shipment to FAIR Installation in building Bringing into service /commisioning – Are we able to guarantee this new timeline ? Taking into account: the pausing/blocking of the funds flow, the pausing/blocking of the technical supports, the pausing/stopping of the project in some countries... ? About 1 year of pausing/blocking can be tolerated.... more time is a risk: the detector could’t be finisched by FAIR ? past new

…but from a point of view of all the work packages There is a interlaced division of work packages among the three participating groups that would make it difficult to continue the project if one of the groups comes out completely from the project. In fact, the redistribution of the works on the remaining groups would be very heavy in terms of cost, man power, expertise and deadlines x

From a technical point of view… Pixel and strips silicon devices can be confirmed for the installation in 2021 but concerning ToPix, the pixel readout, we have to avoid ‘the sword of Damocles’ (italian phrase) of IBM technology and its corresponding short availability. Our advice to get around this hitch: migration to a new CMOS technology 130 nm TSMC could be the best choice in terms of present and future technology (used also for the upgrade of LhcB) radiation tolerance, already tested at CERN ToPix4 can be translated to the new technology The cost of the new prototype + Eng. Run in 130 nm CMOS TSMC < the cost of the Eng. Run in 130 nm CMOS IBM

In the middle of many difficulties, the work is ongoing…

PASTA and chip carrier for the strip part Layout of the new version of the chip carrier board Photograph of a PASTA prototype PASTA on the power test board DAQ system under development by the Julich group

Single chip assembly and ToPix4 characterization ToPix4 + epitaxial sensor Pixel tracking station SEU effects Efficiency ToT with respect to the discharge current of the feedback capacitor

Cooling test of a strip stave stave Strip sensor Dummy resistor Thermal map

DCDC circuits test setup Prototype of a block of 88 DCDC circuits Cooling simulations: DCDC block Resistive load MVD services, around the beam pipe Resistive load

Optoelectronic board and cable section Optoelectronic board Evaluation of cable cross section Cooling simulation: optoelectronic board stave

FEM and mechanics details FEM for the external frame of the new layout with two separated strip disks Half MVD equipped with cooling pipes

Spares

From SG report 5.7. MVD System manager: Daniela Calvo The MVD is an essential detector for the PANDA experiment. It is supported by groups of FZ Jülich, Gießen University, FH SWF Iserlohn, INFN Torino and Torino University. In addition there is cooperation with CERN on several components. The TDR was received in Feb 2013, approved in fall The referees had no severe criticism concerning its realization. The proposed pixel and strip detectors are widely used. Extensive beam tests have been performed at CERN and at COSY in order to show that the requirements can be met. The detector, including support structures, cables, power and cooling lines, has been fully implemented in CAD. The MVD is fully implemented in the PANDA simulation framework. All active and passive components are available including cooling structures, cables and passive electronic elements down to single SMD parts. The overall amount of material is in good agreement with that expected in the final design. The reconstruction code of the MVD has been developed. Different algorithms for cluster finding and fitting as well as standalone track finding and fitting are available in an event and time-based version. This code has been tested with test beam data proving its usefulness for real measured data. The total requested money for the MVD is 5.9 M€. Of this 2.3 M€ are available to be spent now or secured by firm commitments (Jülich-Hessen). 2.6 M€ should come from Torino. About 1 M€ still have to be asked for. The funding profile peaks in the years 2016 – 2018 The total manpower available for the MVD is 25 FTE's. If the sensors and the data acquisition components arrive as planned, that manpower should be sufficient to complete the detector by Risk assessment: Serious problems for the production of the sensors could arise when the money is delayed because the CERN-IBM contract presently ends at the end of The dense package of signal cables and power lines, required by the backward end-cap calorimeter, could become a problem. A partial installation followed by a later completion is not seen as an option due to the strong interrelation of the vacuum pipes, the MVD and the STT inside the central mounting frame. The discontinuation of the sensor production technique at CERN asks for an early procurement as well. TDR, submitted to the Coll.: Dec Approuved: Feb !

PASTA features Key featuresValue Channels64 Input pitch 63  m Clock frequency160 MHz Rate capability100kHz/ch Power consumption< 4 mW/ch Front-end noise< 600 e- Time bin width ps Charge resolution8 bit (dyn. range) Radiation tolerance100 kGy

Data acquisition system Testing board with the assembly Xilinx Evaluation Board equipped with a Virtex 6 FPGA clock signal reset signal Network connection 1^ DAQ based on LabVIEW Control2^ DAQ to manage higher rates under development Global Control push FPGA Board with DUT FairMQ MUX JDRS Datamonitor sub JDRS Receiver sub pu ll pu b pull JDRS Main Software push pull Write to Disk JDRS Receiver JDRS Receiver sub pull Write to Disk

DCDC circuits test setup Prototype of a block of 88 DCDC circuits Cooling simulations: DCDC block Rack – power supplies Cooling system Resistive load

Al cable and hybrid hybrid 1.5 m long cable To oscilloscope PRBS from pulse generator SLVS signals Multilayer hybrid made of Aluminum