VHDL Workshop FSM. FSM-Smart Counter Requirements Receives a start signal. When start signal goes high, starts to count from zero: reset value – 0, first.

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Presentation transcript:

VHDL Workshop FSM

FSM-Smart Counter Requirements Receives a start signal. When start signal goes high, starts to count from zero: reset value – 0, first clock after start – Out = 1, second clock after start- 2 etc. Counts until a user defined value. When finished, issues a Finish pulse and waits for a new start. Can receive a pause signal active high. In this case, will wait until pause goes down, and then continue

FSM-Top Level

FSM - Design Idle state Count state Pause state Pause = ‘0’ Pause = ‘1’ Start rising and pause = ‘1’ Start rising and pause = ‘0’ Finished counting

FSM – Writing Code Declare states used for FSM FSM divided into two processes: Synchronous – saves next state Asynchronous – decides where to go, control signals We use other processes for help

FSM – Declaration and Sync Process Which are FF’s and which are just wires?

FSM – Aiding process

FSM- Async Process Defaults Assignment at every branch

FSM- Async Process-continued

FSM- Test Bench

FSM – Test Bench - continued

FSM- in action

FSM - summary Before writing – design Divide into two processes Define states with meaningful names Every signal (wire) must have: An assignment in all possible branches, or Default assignment