EE/CS 480 Spring 2008 1February, 2008 University of Portland School of Engineering Project Golden Eagle Fast Fourier Transform Processor Team Sandra Pellecer.

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Presentation transcript:

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Project Golden Eagle Fast Fourier Transform Processor Team Sandra Pellecer Neil Tuttle Ziyuan Zhang Advisor Dr. Inan, Dr. Osterberg Industry Representative Mr. David Dunning Intel

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Overview Introduction Scorecard Additional Accomplishments Plans Issues/Concerns Conclusions

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Introduction MOSIS chip to perform FFT algorithm Designed to improve speed of digital signal processing Applicable in all areas involved with digital signal processing

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip Block Diagram

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 1 B 2 Logic Layout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 1 L-EDIT Layout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 1 Pinout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 2 B 2 Logic Layout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 2 L-EDIT Layout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Chip 2 Pinout

EE/CS 480 Spring February, 2008 University of Portland School of Engineering System Block Diagram

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Flowchart

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Prototype Schematic

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Scorecard Theory of Operations 1.0 (2/12/08)

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Additional Accomplishments Wire-wrapped CPLDS and reprogrammed them RS232 Communication (PIC) I 2 C Communication (PIC)

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Plans Microprocessor programming –Test LCD –Interface CPLD with PIC –A/D Converter CPLD digital logic simulation and testing Wait for MOSIS chips –ETA around spring break.

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Milestones (Fall) Functional Spec 1.010/5/200710/12/200710/5/2007 Project Plan 0.910/26/2007 Project Plan 1.011/9/2007 Send design to MOSIS11/22/ /9/2007 Theory of Operations approval 2/22/2008 NumDescription Original 10/30/07 Previous 11/27/07 Present 02/05/2008 1Product Approval09/07/2007 2Functional Spec 0.909/21/2007 3Completed Chip 109/24/2007 4Functional Spec 1.010/05/2007 5Completed Chip 210/24/2007 6Project Plan 0.910/26/2007 7Project Plan 1.011/09/2007 8Send design to MOSIS11/22/2007 9Design Review12/04/ Check LCD functionality12/04/ Convert C1 to ABEL01/20/ /18/ Convert C2 to ABEL01/31/ /24/2007

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Milestones (Spring) Functional Spec 1.010/5/200710/12/200710/5/2007 Project Plan 0.910/26/2007 Project Plan 1.011/9/2007 NumDescription Original 10/30/07 Previous 11/27/07 Present 02/05/08 13FW: RS232 functional2/10/2008 2/19/ Theory of Operations2/22/20082/15/20082/12/ Prototype completed2/29/ FW: Graphics functional3/10/ Final firmware revision3/31/2008 3/10/ MOSIS chip function testing3/18/ Final project assembly3/28/ Presentation PPT Completed4/6/ Founder’s Day4/8/ Postmortem4/23/ Final Report4/25/2008

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Concerns/Issues Might discover errors during CPLD testing –If there is a problem with the MOSIS chips, we will use the CPLDs instead.

EE/CS 480 Spring February, 2008 University of Portland School of Engineering Conclusions In Progress: Continue working on PIC firmware and CPLD testing. Questions?