First measurements of the Gossipo-3 CERN, Geneve March 24, Vladimir Gromov NIKHEF, Amsterdam, the Netherlands

Timepix-2 V.Gromov224/03/10 technology: 0.13μm CMOS - pixel: 60μm x 60μm - event clock: 40MHz - accuracy (bin size): 1.73ns - range: 102μs 25ns) - ToT accuracy: σ = 200e - (27ns) - ToT range: 6.4μs - Hit Counting mode - noise: σ = 70e - - fast response: 20ns (rise time) - power (goal): 100mW/cm 2 (3μW/ch) Gossipo-3: main features Front-end (preamp, comp) Ingrid preamp Pixels (preamp, comp, Threshold DAC, high resolution TDC,counters & control logic) Bias generating circuit LDO (generates controllable Power Supply Voltage for Ring oscillators )

Timepix-2 V.Gromov324/03/10 Gossipo-3: Test set-up S3 Multi IO Board (general purpose test board designed by Bonn group) USB port G3 Testboard (dedicated for Gossipo-3 chip )

Timepix-2 V.Gromov424/03/10 Gossipo-3: front-end circuit Time Uin Uin + 70mV Uin + Qin / Cfb -Time ● Isat Tfb /Cfb exp[-Time/(Cfb ● Ron Tfb )] Uout Tfb in saturationTfb in triode - no leakage compensation - constant current feedback (1nA) - high gain (1mV / fF) - low power consumption (3μW/ch) - fast response (20ns) - low noise (σ =70 e - ) - channel-to-channel threshold spread (σ =70e - no equalization) (σ = 5e - with equalization C par ≈ 10 fF Tfb Cfb =Cds+Cdg+Cdb+Cdj ≈ 1 fF Input pad (22μm x 22μm) OPAMP Discharge protection Ib = 6nA 2.4/ /2.4 U out_preamp 2nA U THR_common Vdd_ana 2.4/ /2.4 U THR_pixel Discr. Baseline recovery U out_discri Ron = 100MΩ C test ≈ 1.3 fF U test Metal-to-metal parasitic capacitance ncap C=170fF

Timepix-2 V.Gromov524/03/10 Gossipo-3: preamp output Qin = 375 e - ( 46mV ● 1.3fF= 60aC) simulations measurements Noise is very low

Timepix-2 V.Gromov624/03/10 Preamplifier output: channel-to-channel gain mismatch Channel#1 Channel#2 Channel#3 Utest ● Ctest1/Cfb1 Utest ● Ctest2/Cfb2 Utest ● Ctest3/Cfb3 Ctest and Cfb are good reproducible Feedback time constant varies a lot

Timepix-2 V.Gromov724/03/10 Front-end circuit output: Time-over-threshold mismatch Channel#1 Channel#2 Channel#3 ToT1 ToT2 ToT3 ToT channel-to- channel mismatch is around 50%

Timepix-2 V.Gromov824/03/10 Front-end circuit output: internal time delay and jitter 370 e - fast signal 1000 e - fast signal 370 e - slow signal jitter Internal delay,ns Signal size, e - ∆t min = 9ns

The front-end Main specifications:Main specifications: - low power consumption (3μW/ch) - fast response (20ns) - low noise (σ =70 electrons) - channel-to-channel threshold spread (σ =70 electrons) Vdd_ana Input stage 720 nA Ron = 30MΩ 0.48/2.4 U out_preamp 435 nA 70 nA 2.4/2.4 Preamp_in 1fF C par ≈ 10 fF 6 nA Voltage follower Feedback gm=23u C*= 6f T fb sub_preamp (0.2V) 5/0.24 2nA U THR_common Vdd_ana 2.4/ /2.4 U THR_pixel Discr. Baseline recovery U out_comp ncap C=170fF Ron = 100MΩ

Timepix-2 V.Gromov1024/03/10 Thermal Noise: measurements and simulations Measurements: Qin = 375 e - = 60mV ( 46mV ● 1.3fF= 60aC) ENC = 25e e - ●4mV / 60mV 20mV p-p → σ = 4mV 20mV 60mV Simulations: 64mV 4.2mV ENC = 24.6e e - ●4.2mV / 64mV

Timepix-2 V.Gromov1124/03/10 Thermal Noise: hand calculations Cd = Cp+Cgg T1 + Cdd Tprot + Cjd Tprot = 15fF 7.4fF+5.7fF+0.4fF + 1fF Cl = Cgg T4 + Cdd T3 + Cjd T3 +Cdd T2 + Cjd T2 = + Cp= 6.5fF 1.1fF+0.6fF+1.7fF + 0.4fF +1.1fF + 1.6fF=6.5fF Cf = 1fF gl = gds T3 +gds T1 ●gds T3 / gm T3 = 0.22u 0.17u + 1u ● 1u / 20u ENC 2 = γ ● k ● T ● ( Cd + Cf ) ● Cf / Cl = 9.6 ● ≈1 =1.3 ● ≈300 ≈15 ● ≈1 ● ≈6.5 ● ENC ≈ 20e -

Timepix-2 V.Gromov1224/03/10 Thermal Noise: σ n = 4mV can be true? =1.3 ● ≈300 Uout C d =15fF Cf= 1fF H(jw) = 4kT ● gm -1 ●df = S n ●df H(jw) = [gm/gl] / [1+jw●Cl / gl] w 0 dB gm / Cl gm / gl U n out(jw) = U n ● H(jw) ● {1+ H(jw) ● [1+Cd/Cf] -1 } -1 = S n ● ∫ │ h(j2πf) │ 2 df = 4 ● k ● T ● (1/gm) ● ∫ │ h(j2πf) │ 2 df = 8.6 ●10 -6 ≈ 3mV 1+ Cd/Cf DC open loop gain DC closed loop gain w cut-off 1.1 ●10 10 =20u = 0.22u ≈6.5 ● =20u β h(jw) |H(jw)| |h(jw)| low Cf |h(jw)| high Cf Freq., Hz [ ∫ │ h(j2πf) │ 2 df ] 0.5 Cf = 1fF Cf = 2fF Cf = 4fF Cf = 8fF U n out ~Cf -1/2

Timepix-2 V.Gromov1324/03/10 Threshold mismatch Vdd_comp Comparator 900 nA Inverters Comp_inComp_out 0.8/1.2 Thr Vbias T1 0.9/0.24 T2 0.9/ / / / 0.24 Measurements: ∆U Thr = 50mV p-p σ = 15mV Simulations: σ = 5.6mV ● √ 2● (W T1,2 ● L T1,2 ) -1 σ = 17mV (100e - ) 50mV U Thr Entries Preamp_out 0 nA

Timepix-2 V.Gromov1424/03/10 Qin measurements: ToT method Uout charging discharging Uout,V Time, μsec C par =15fF Cfb= 1fF OPAMP Ib = 1nA Qin Qin=400e - … 20000e - ToT threshold Uin,V Uin A: Qin is deposit on Cfb : ∆Uout=0.85V-0.42V ∆Qin= ∆Uout ● Cfb= 0…3 Ke - Uin=420mV Uout = 420mV…850mV B: Qin is deposit on C par : ∆Uin=0.42V-0V ∆Qin= ∆Uin ● C par = 0…30 Ke - Uin=420mV…0V Uout = 850mV Ib discharges the capacitors ToT dynamic range ~ C par ToT (Qin) = Qin / Ib

Timepix-2 V.Gromov1524/03/10 Time-over-threshold measurements Qin, e - ToT, ns measurements simulations channel-to-channel ToT mismatch ~ 40% threshold ToT mismatch ~ 40% Monte Carlo simulation: mismatch only Uout,V Mismatch of the feedback current Ib limits reproducibility of the TOT slope ~ 0.2ns/e -

Timepix-2 V.Gromov1624/03/10 ToT measurements: how to improve mismatch Tfb OPAMP Ib = 6nA 2.4/ /2.4 Uout Qin Uin Id sat = 2●n●β●U T 2 ● exp[(Ugs- Uthr)/(n●U T ) ] d(Id sat )/dβ = Id sat /β → σ{∆(Id sat )/Id sat }=σ{∆β/β} = 1.82% / √(W ● L ) d(Id sat )/dUthr = Id sat / (n●U T )] → σ{∆(Id sat )/Id sat } = σ{∆ Uthr / n●U T } = 2.86mV/[30mV ● √(W ● L )]= 9.5% / √(W ● L ) = 9% =2.4μm =0.48μm → A β [% / μm] !!! Statistical spread ~ 1 / √(W Tfb ● L Tfb ). By making the feedback transistor larger we improve matching but increase Csd → gain degradation

Timepix-2 V.Gromov1724/03/10 Accuracy of the ToT measurements σ(jitter) = σ(Uout noise )/ [dU/dt] ≈ 4mV ≈ 0.3mV/ns ≈12ns time jitter = 80ns threshold Preamp Output Comparator Output dU/dt = 0.3mV/ns noise = 4mV RMS jitter ≈ 80ns p-p (400e - )

Timepix-2 V.Gromov1824/03/10 Ring oscillator configurations Voltage controlled RO RO_out 0.78/0.18 RO_en RO_cntr NAND RO_out RO_en RO_cntr NAND Vdd Current controlled RO 2.1/ / / / RO_en RO_cntr NAND Vdd Current controlled “differential” RO 48/ / / RO_out U_cntr I_cntr start Start-up distortions

Timepix-2 V.Gromov1924/03/10 Voltage controlled Ring oscillator RO_out 0.78/0.18 RO_en RO_cntr NAND 2.1/ U_cntr I_cntr U_cntr V, slope T_osc, ns ps / mV I_cntr, μA μA / mV Control characteristic Basic properties SpecificationValueComments ∆T_osc / ∆Vdd (∆U_cntr)- 4.7ps / mV ( 0.3% / mV) ∆U_cntr < 20mV is tolerable → ∆T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC ∆T_osc / ∆Temp+0.32ps / ° C (0.02% / ° C) T_osc, U_cntr (Fast corner=6, FFF, 27°C)1.71ns / 614mV T_osc, U_cntr (Typical corner=1, TT, 27°C) 1.72ns / 737mV T_osc, U_cntr (Slow corner=7, SSF, 27°C)1.7ns/ 930mV Channel-to-channel mismatch (Total active area (W●L) of the delay FET’s 6% 5.18 μm 2 T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC

Timepix-2 V.Gromov2024/03/10 Current controlled Ring oscillator Control characteristic Basic properties SpecificationValueComments ∆T_osc / ∆Vdd-0.5ps / mV (0.04% / mV) ∆U_cntr < 150mV is tolerable → ∆T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC ∆T_osc / ∆V wire 13ps /mV (0.8%/mV) ∆V wire < 7mV is tolerable → ∆T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC ∆T_osc / ∆Temp+0.64ps / ° C (0.04% / ° C) T_osc, I_cntr (Fast corner=6, FFF, 27°C)1.7ns / 31 μA T_osc, I_cntr (Typical corner=1, TT, 27°C )1.7ns / 43μA T_osc, I_cntr (Slow corner=7, SSF, 27°C)1.7ns / 62 μA Channel-to-channel mismatch (Total active area (W●L) of the delay FET’s 6% 5.18 μm 2 T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC RO_out RO_en RO_cntr NAND Vdd 24/ / / U_cntrI_cntr R_wire I_cntr, μA slope T_osc, ns ps/μA U_cntr, V mV/μA gds active =13μ gm active = 600u gds_sat active =170mV 24/0.4

Timepix-2 V.Gromov2124/03/10 Current controlled “differential” Ring oscillator Control characteristic Basic properties I_cntr R_wire RO_en RO_cntr NAND Vdd 48/ / / RO_out U_cntr I_cntr I_cntr, μA slope T_osc, ns ps/μA U_cntr, V mV/μA SpecificationValueComments ∆T_osc / ∆Vdd-0.3ps / mV (0.02% / mV) ∆U_cntr < 300mV is tolerable → ∆T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC ∆T_osc / ∆V wire 16ps /mV (1%/mV) ∆V wire < 6mV is tolerable → ∆T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC ∆T_osc / ∆Temp+0.64ps / ° C (0.04% / ° C) T_osc, I_cntr (Fast corner=6, FFF, 27°C)1.72ns / 75 μA T_osc, I_cntr (Typical corner=1, TT, 27°C )1.7ns / 105μA T_osc, I_cntr (Slow corner=7, SSF, 27°C)1.71ns / 155 μA Channel-to-channel mismatch (Total active area (W●L) of the delay FET’s 4% 2.75 μm 2 T_osc < 6% (less than one T_osc (1.71ns) for 16 clocks in a 4 bit TDC gds active =30μ gm active = 1.3m gds_sat active =180mV 48/0.4

Timepix-2 V.Gromov2224/03/10 Choice of the Ring oscillator Comparison table SpecificationVoltage-controlled Ring Oscillator Current-controlled Ring Oscillator Current-controlled “differential” Ring Oscillator Sensitivity to the Power Supply Voltage shift ∆T_osc / ∆Vdd 0.3% / mV (Control voltage) 0.04% / mV Best 0.02% / mV Good Sensitivity to the current-related Voltage drop ∆T_osc / ∆V wire 0.3% / mV Normal 0.8%/mV High 1%/mV High Sensitivity to the Temperature instability ∆T_osc / ∆Temp 0.02% / ° C Low 0.04% / ° C Good 0.04% / ° C Good Channel-to-channel mismatch6% p-p Acceptable 6% p-p Acceptable 4% p-p More than acceptable Current (when active)42μA Low 43μA Low 105μA High Areaminimumincreased by PFET (24μm x 0.4μm)increased by PFET (48μm x 0.4μm)

Timepix-2 V.Gromov2324/03/10 Ring oscillator: mismatch and power Input Output 3W/L R on =1/[µ ● C ox ● (W/L) ● (V gs -V thr )] Input GND VDD Output DELAY β C*C* N inverters σ(∆ β/ β) = 2% ● (W ● L) -0.5 σ(∆ Vthr) = 5mV ● (W ● L) -0.5 σ(∆DELAY/DELAY) ≈ 2% ● (N●W ● L) -0.5 W/L 3W/L W/L DELAY ≈ N●3●R ox ●C* R on ~ L/W C * ~ L ● W DELAY = R ox ● C* = inv (W ) Power ~ C* ~ W Area ~ W Mismatch ↓ Power ↑ ← W↑ Area ↑ = 0.78μ = 0.18μ = 10≈ 2%

Timepix-2 V.Gromov2424/03/10 Voltage drop effect Pixel_1 Pixel_2 Pixel_128 Pixel_255 Pixel_ cm 50Ω Bus (Vdd_osc) 10μm width M1 R = 0.07Ω●0.7cm/10μm = 50 Ω ∆U = 0.5 ● 50Ω ● 155μA = 4mV 0.7cm 50Ω I vdd worst case = 62μA (voltage –controlled RO) I vdd worst case = 66μA (current –controlled RO) I vdd worst case = 155μA (current –controlled “differential” RO)

Timepix-2 V.Gromov2524/03/10 Power supply source for the Ring Oscillators Input conditions: Sensitive area: 1.4cm x 1.4cm (1.96cm 2 ) Pixel size: 55μm x 55μm Number of pixels: 256 x 256 (65 536) Track occupancy: 12 (cm 2 ●BX) -1 Tracks per chip per BX (Ntr) : 24 Fluctuation of the number of the tracks per chip per BX: σ tr = √N tr = √24 ≈ 5 Average primaries per track: 10 Active pixels (number of primaries) per BX (Nact): 240 Current per active pixel (Iosc): 100μA Specification of the LDO: Average load current: Iav = 24mA = Nact● Iosc = 240●100μA Peak load current (worst case): Ipeak = 44mA= Iosc ●10 ●(N tr +4●σ tr )= 100μA ● 440 Output impedance: Zout = 7 Ω= ∆150mV / ∆ 20mA tolerable voltage drop load current jump (worst case) 55μm 256pixels · 55μm =1.4cm Readout chip N tr =24 Entries Standard deviation σ tr ≈ 5 The highest track occupancy: N tr +4●σ tr = 44

Timepix-2 V.Gromov2624/03/10 Gossipo-3:on-chip voltage regulator Functionality - tunes oscillation frequency - power supply ripple rejection - temperature compensation - low output impedance in wide frequency band Opamp Off-chip cap 10μF Vdd=1.2V 1.14k 2k U vdd_osc (0.6V…1.1V) Uref

Timepix-2 V.Gromov2724/03/10 Oscillator inverters powered by vdd_osc (0.64V…1.1V) Gates powered by vdd_dig=1.2V Coexistence of 1.2V logic domain and 0.64V logic domain. Level shifter (40μA extra current in the time of oscillation activity) Gossipo-3:oscillator circuit start_osc stop_osc

Timepix-2 V.Gromov2824/03/10 Gossipo-3:oscillator circuit on the pixel Oscillator 25μm x 10 μm Logic: counters & control Analogue Front-end DAC

Timepix-2 V.Gromov2924/03/10 Gossipo-3 : ideal oscillation frequency en_osc start_oscstop_osc out_osc 25ns (max) Final State of the Counter State = 14 (max for LFSR) delay fb delay fb = 25ns/29 = 0.862ns → T osc ideal = 2 ● delay fb = 1.724ns arrival time of the stop_osc signal T osc ideal

Timepix-2 V.Gromov3024/03/10 Gossipo-3: operation of the oscillator circuit en_osc (start) stop out_osc state “0” out_osc state “1” stop out_osc state “1” stop out_osc state “2” out_osc state “2” Counter clock

Timepix-2 V.Gromov3124/03/10 Gossipo-3: operation of the oscillator circuit net_A net_B net_C net_D stop_osc start_osc out_osc 25ns (max) clk +125ps ?? stop_osc start_osc +60ps net_A net_D net_B +60ps +820ps +120ps net_C out_osc +60ps

Timepix-2 V.Gromov3224/03/10 Gossipo-3: threshold DAC Analogue Front-end DAC No power consumption I tail =5μA U THR_pixel a _a b _b c _c On-pixel Switch tree (19.5μm x 3.7μm) with 30 FET’s (4bits) Voltage generator shared between pixels R 16 =1.5kΩ U THR_com =0.4V R 15 =1.5kΩ U1=0.408V U2=0.416V U16=0.525V Minimum size PFET’s : W/L= 0.16μm / 0.12 μm Vgs on = 0.4V / Vthr =0.51V → Ron= 1.7 MΩ !!! Ron=1.7MΩ Sensitive to the leakage currents (parasitic loads) leakage Possible solution: replace pfets (Ron=1.7MΩ) with nfets (Vgs on = 0.475V / Vthr =0.676V → Ron=10kΩ)

Timepix-2 V.Gromov3324/03/10 Timepix2: charge sensitive preamplifier Timepix2 Pixel size55 µm x 55 µm Analog pixel area (see Figure 2)55 µm x [10…20] µm Pixel matrix256 x 256 Input chargeBipolar (h+ and e-) Leakage current compensationYES Peaking time≤ 25ns Return to zero (Tunable)< 5 Ke- TOT linearity and range< 500 Ke- Preamp output linear dynamic range< 40 Ke- Return to zero full chip spread (TOT spread)< 5% ENC (σ ENC )~75 e- Detector capacitance< 50 fF # Thresholds1 Discriminator response time< 2ns Full chip minimum detectable charge< 500 e- Threshold spread after tuning (see Figure 1)< 30 e- Pixel analog power consumption< V Uout = 0.6V Cpar Cfb Ib Qin Uin = 0.6V It Vdd=1.2V Bipolar (h+ and e-) → Output Dynamic Range = 0.5V (0.6V ± 0.5V with Vdd=1.2V, Vds sat =0.1V) Preamp output linear dynamic range = 40ke - (6fC) → Cfb = 12fF = 6fC / 0.5V TOT linearity and range = 500ke - (80fC) → Cpar = 145fF = (80fC-6fC) / 0.5V (Uin > +0.1V) Detector capacitance: Cpar < 50fF (contradiction) ENC (σ ENC ) = 75e - (0.012fC) → Cl = 51fF ENC= [k ● T ● ( Cd + Cf ) ● Cf / Cl] 0.5 = [1.3● ● 300 ● (145● ● ) ● 12● / 51 ● ] 0.5 Peaking time ≤ 25ns → τ a = 5ns → gm = 133μ → It= 5μA = gm / 27 → Power preamp = 6μW τ a = [Cl/gm]●( Cd + Cf ) ● Cf Return to zero (Tunable) < 5 Ke- (0.8fC) → Ib sat = 0.8nA = 0.8fC / 1μs Return to zero full chip spread (TOT spread) < 5% → σ{∆(Ib sat )/Ib sat = 1% → W ● L = 100 μm 2 Cl σ{∆(Ib sat )/Ib sat } = σ{∆ Uthr / n●U T } = 2.86mV/[30mV ● √(W ● L )]= 9.5% / √(W ● L )

Timepix-2 V.Gromov3424/03/10 Timepix2: fast discriminator Vdd_comp Voltage comparator: Gossipo3 900 nA In 0.8/1.2 Thr Vbias T1 0.9/0.24 T2 0.9/ / / / nA Thr Vb2 Vb3 Vb4 In Out 0.3/ / / / /6.13 Current comparator: Medipix3 Low High 1μA ??? 0.2μA ??? 50nA ???