Integration with ATLAS DAQ Marcin Byszewski 23/11/2011 RD51 Mini week Marcin Byszewski, CERN1

Outline FEC zero suppression Integration with ATLAS DAQ 23/11/2011 RD51 Mini week Marcin Byszewski, CERN2

FEC zero suppression APV25 – analogue, 128 channels * number of time samples FEC FPGA firmware module – by R. Giordano and S. Martoiu – Possibility to bypass for a single APV25 chip (configure stages) – Configuration (pedestal measurement) must be run by user – Passed first tests with the mmDAQ – Remotely controlled by DCS (by G. Iakovidis) – Finishing debugging stage – Max rate not tested – Limits number of time bins to ~16 23/11/2011 RD51 Mini week Marcin Byszewski, CERN3

FEC zero suppression Based od mmDAQ ZS Suppression cut: Q sum / N time_bins < Ped stddev * A Q sum = sum of charge N time_bins = number of time samples Ped stddev = Pedestal std.dev. A = user defined factor (about 0.8 in mmDAQ) 23/11/2011 RD51 Mini week Marcin Byszewski, CERN4 APV signal time

FEC zero suppression Data Format: typedef char BYTE; // 8-bit word typedef unsigned int WORD32; // 32-bit word typedef unsigned short int WORD16; // 16-bit word struct APV_HEADER { BYTE APV_ID; // APV Identifier number on the FEC card (0 to 15) BYTE N_CHANNELS; // the number of channels which will be following the header BYTE N_SAMPLES; // the number of samples per channel BYTE ZS_ERROR; // Error code from the Zero Suppression Block, meaning have to be defined WORD32 RESERVED; // 32 bits reserved for future use }; struct CHAN_INFO { BYTE RESERVED; // 8-bits reserved for future use BYTE CHAN_ID; // Channel identifier, 0 – 127, future: 128 common mode, 129 for error codes WORD16 CHANDATA[N_SAMPLES]; // 16 bit words, actual data will be 13-bits wide }; 23/11/2011 RD51 Mini week Marcin Byszewski, CERN5

Micromegas in winter shutdown Plan to install during this Xmas shutdown: – 8x9 cm MBT0 chamber on the edge of MBTS – 1.2x0.5m 2 test chamber (4 active planes, X+U strips) HW – All equipped with APV25 chips (4 + 4*10 = 44 chips) – 25 m HDMI cables (to be 5V) – 4-5 FECs – DTC links to 1 SRU unit – Optical S-Link fibre to a ROS in USA15 cavern Marcin Byszewski, CERN6 23/11/2011 RD51 Mini week

Current MAMMA’s Lab setup Marcin Byszewski, CERN7 mmDAQ ZS SRS DCS mmDAQ ZS SRS DCS 16x APV25 Trigger Raw data out FEC HDMI 23/11/2011 RD51 Mini week DCS Ethernet

Integration into ATLAS DAQ Marcin Byszewski, CERN8 mmDAQ ZS mmDAQ ZS 16x APV25 Trigger Raw data out FEC 44 APV25 44 APV25 FEC SRU DTC HDMI optical ATLAS ROS ATLAS ROS Data out LVL1 Accept Ethernet DCS LVL1 Accept 23/11/2011 RD51 Mini week

Marcin Byszewski, CERN9 Integration Challenge 1: FPGA FW 44 APV25 44 APV25 FEC SRU ZS DTC HDMI Enormous software development effort on a short time Napoli, CERN DTC Event builder DCS S-Link optical ATLAS ROS ATLAS ROS Data out LVL1 Accept Ethernet DCS LVL1 Accept DTC Missing FPGA firmware 23/11/2011 RD51 Mini week Raffaele Giordano Andre Zibell Vincenzo Izzo Sorin Martoiu

23/11/2011 RD51 Mini week Marcin Byszewski, CERN10 SRU FW blocks for ATLAS DAQ To FECs To ROS Read DTC into input buffer Read DTC into input buffer SRU Event building DCS S-Link Data out S-Link Data out DTC links DTC links data Slink HW Slink HW L1 trigger forwarding On/Off To PC Ethe rnet DCS L1 trigger TTCrx Event data

Integration Challenge 2: Timings Marcin Byszewski, CERN11 23/11/2011 RD51 Mini week total time (us) time pertotalnumber of timebins0 step(1tb) LVL1 trigger arrives at SRU trigge r SRU- >FEC- >APV APV ->FEC readout 7798 APSP 4x70clocks = 7us / timebin 3,510,549147output140bits*clock = 3500 ns /timebin 10, ,311,818,2165,2FEC zero suppression (parallel) 11,80165,2 11,80165,2FEC -> SRU data transmission (parallel FECs A.)DTC link speed 10,6822,5 149, ,714strips=224bits=28bytes 22,50314,7SRU Event Building 22,50314,7 22,50314,7SRU->ROS S-Link transmission 0,5023,00,5321,75,5nsec/m90m=0,50us

Integration: Challenge 2 Marcin Byszewski, CERN12 44 APV25 44 APV25 FEC SRU ZS DTC HDMI Ok for 1 time sample, but we want to send 16 time samples.  Do not provide data for every LVL1 Accept DTC Event builder DCS S-Link optical ATLAS ROS ATLAS ROS Data out LVL1 Accept Ethernet DCS LVL1 Accept DTC  Synchronous data (13us)  Synchronous data (13us) APV ->FEC readout timing APSP4x70clocks = 7us / timebin output140bits*clock = 3500 ns /timebin 16 time bins -> 220us 23/11/2011 RD51 Mini week TTC Raffaele Giordano Andre Zibell Vincenzo Izzo Sorin Martoiu

ROS LV1 handler Processing data? NO Set to YES Forward LV1 to FEC Return event to ROS (empty) SRU forward LV1 FEC readout APV Zero suppression time LV1 ID 1 (LVL1 ID2) +200us ROS LV1 handler Processing data? YES Store reference Do not forward trigger (LVL1 ID5) Build & Store Event Set Processing data to NO Build & Store Event Set Processing data to NO ROS LV1 handler Processing data? NO Set to YES Forward LV1 to FEC Return event to ROS (BCID1) SRU stores references of the incoming LVL1. When finished processing it sends out the processed event and dummy responses to LVL1 received in the mean time. (LVL1 ID1) (LVL1 ID5) (…) <- to ROS 23/11/2011 RD51 Mini week Marcin Byszewski, CERN13 LVL1 handling scheme

Integration: Challenge 2 Marcin Byszewski, CERN14 44 APV25 44 APV25 FEC SRU ZS DTC HDMI DTC Event builder DCS S-Link optical ATLAS ROS ATLAS ROS Data out LVL1 Accept Ethernet DCS LVL1 Accept DTC  Synchronous data (13us)  Synchronous data (13us) APV ->FEC readout timing APSP4x70clocks = 7us / timebin output140bits*clock = 3500 ns /timebin 16 time bins -> 220us 23/11/2011 RD51 Mini week TTC Raffaele Giordano Andre Zibell Vincenzo Izzo Sorin Martoiu 160MBit/s FEC -> SRU data transmission (parallel FECs A.)DTC link speed160Mbit/s =20MB/s =DTC link speed20,97bytes/us 14strips=224bits=28bytesx number of chips in FEC10=DTC transmission 1 tb13,35us

Summary progress to prepare for ATLAS DAQ integration this winter Marcin Byszewski, CERN15 23/11/2011 RD51 Mini week

Backup slides 23/11/2011 RD51 Mini week Marcin Byszewski, CERN16