ECE 448 Lab 3 FPGA Design Flow Based on Xilinx ISE and Isim. Using Seven-Segment Displays, Buttons, and Switches.

Part 1: Distribution and testing of FPGA boards Part 2: Seven Segment Displays Part 3: User Constraints File Part 4: Buttons and Switches Part 5: Introduction to FPGA Design Flow based on Xilinx ISE Part 6: Introduction to Lab 3 Part 7: Class Exercise Agenda for today

Part 1 Distribution and Testing of FPGA Boards

Part 2 Seven Segment Displays

4-Digit Seven Segment Display

Patterns for Decimal Digits

Patterns for Hexadecimal Digits

Connection to FPGA Pins

Multiplexing Digits

Time-Multiplexed Seven Segment Display

Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement

Size of the counter 1 ms ≤ 2 k * T CLK ≤ 16 ms f CLK = 100 MHz k = ?

Part 3 User Constraint File (UCF)

File contains various constraints for Xilinx – Clock Period – Circuit Locations – Pin Locations Every pin in the top-level unit needs to have a pin in the UCF

User Constraint File (UCF) - SSD # Seven Segment Displays NET " SEG " LOC = "T17" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "T18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "U17" | IOSTANDARD = "LVCMOS33 " ; NET " SEG " LOC = "U18" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "M14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "N14" | IOSTANDARD = "LVCMOS33"; NET " SEG " LOC = "L14" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "N16" | IOSTANDARD = "LVCMOS33"; NET " AN " LOC = "N15" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P18" | IOSTANDARD = "LVCMOS33 " ; NET " AN " LOC = "P17" | IOSTANDARD = "LVCMOS33 " ;

User Constraint File (UCF) - LEDs # LEDs NET "LED " LOC = "U16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V16" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "U15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "V15" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "M11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "N11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "R11" | IOSTANDARD = "LVCMOS33"; NET "LED " LOC = "T11" | IOSTANDARD = "LVCMOS33";

# Buttons NET "CLOCK" LOC = "V10" | IOSTANDARD = "LVCMOS33"; User Constraint File (UCF) CLOCK

Part 4 Switches and Buttons

User Constraint File (UCF) Switches # Switches NET " SW " LOC = "T10 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T9" | IOSTANDARD = "LVCMOS33"; NET " SW " LOC = "V9" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "M8 " | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "N8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "U8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "V8" | IOSTANDARD = "LVCMOS33 " ; NET " SW " LOC = "T5" | IOSTANDARD = "LVCMOS33 " ;

Buttons

Connection of Buttons to FPGA Pins

Debouncing Buttons Bouncing period typically smaller than 10 ms key bounce, t BOUNCE

Using DEBOUNCE_RED to Generate Short Pulses (1) RED – Rising Edge Detector

Using DEBOUNCE_RED to Generate Short Pulses (2)

Debouncer reset input clk output

Debouncer

k and DD Generics k - width of the counter used to measure the debouncing period DD - debouncing period in clock cycles Values of generics given on the next slide assume that the clock frequency = 100 MHz and thus clock period = 10 ns.

k and DD Generics Option 1 (value used for simulation only): DD = 100 assuming bouncing period < 1 μs = 1000 ns condition: DD*10ns = 1000 ns => DD = 100 k=7 because 2^7 > 100 Option 2 (values used for synthesis, implementation, and experimental testing): DD = assuming bouncing period = 10 ms condition: DD*10ns = 10ms => DD = 1,000,000 k=21 because 2^21 > 1,000,000

Rising Edge Detector - RED Turn a step function into an impulse Allows a step to run a circuit for only one clock cycle Rising Edge Detector

clk input output input clk output rising edge detector reset

Connection of Buttons to FPGA Pins

# Buttons NET "BTNS" LOC = "B8" | IOSTANDARD = "LVCMOS33"; BTNS NET "BTNU" LOC = "A8" | IOSTANDARD = "LVCMOS33"; BTNU NET "BTNL" LOC = "C4" | IOSTANDARD = "LVCMOS33"; BTNL NET "BTND" LOC = "C9" | IOSTANDARD = "LVCMOS33"; BTND NET "BTNR" LOC = "D9" | IOSTANDARD = "LVCMOS33"; BTNR User Constraint File (UCF) Buttons

Part 5 Hands-on Session on FPGA Design Flow based on Xilinx ISE and Xilinx ISim

Part 6 Introduction to Lab 3 Automated Teller Machine ATM

ATM Services 1.Balance Inquiry (BAL) 2.Cash Withdrawal (COUT) 3.Deposit Cash (CIN) 4.Deposit a Check (CHEC) 5.Change PIN (CPIN)

Step 1: Entering a PIN Number Default Enter PIN using switches Move to STEP 2

Step 2: Choosing an Option BTNU (UP) BTND DOWN BTNR (RIGHT) BTNL LEFT BTNS (Enter) Default

Balance Inquiry If “Balance Inquiry” chosen first time For Every other “Balance Inquiry”, display the available balance on 7- segment display To go to Step 2 BTNS (Enter)

Cash Withdrawal $10 $20 $100$50 Amount entered using Buttons

Cash Withdrawal If amount entered is not a multiple of $20 or greater than $500, display For Insufficient funds, Display If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the remaining amount is displayed afterwards.

Cash Deposit $10 $20 $100$50 Amount entered using Buttons

Cash Deposit Total deposit amount is displayed on the seven segment display, starting from 0. Available Balance = Previous Balance + Deposit Amount If available balance is greater than the allowed balance ($1500), display and reset the deposit amount to 0. If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

Check Deposit Check value specified in BCD notation entered using Switches. Available Balance = Previous Balance + Deposit Amount If available balance is greater than the allowed balance ($1500), display and reset the deposit amount to 0. If amount entered is a valid amount, it should blink for 5 seconds on the 7-segment display, and the Available Balance is displayed afterwards.

Change PIN New 8-bit PIN entered using Switches If new PIN matches the old PIN, display Otherwise update the new PIN

Part 7 Lab Exercise

16-bit Binary Up-Down Counter

Counter UP COUNTER UP Counter UP q(k-1..k-2) AN Counter UP SEG(6..0) Cou nter UP rst clk OC SSD_DRIVER OC – One’s Complement