Waseda University Low-Density Parity-Check Code: is an error correcting code which achieves information rates very close to the Shanon limit. Message-Passing Algorithm: is an iterative algorithm for decoding LDPC codes, is composed of row operation and column operation. Inherent parallelism of the algorithm makes it suitable for hardware design. Motivation: Requirement is performance gain (bit error performance and data rate) with a small hardware overhead. This Work: Accelerating decoding convergence enables the decoder to improve Bit Error Performance and Decoding Throughput within a limited delay. ASIC Implementation of LDPC Decoder Accelerating Message-Passing Schedule

Waseda University Accelerating Message-Passing Schedule Parity check matrix for hardware sharing Step2Step3 message alpha updated by row operation message beta updated by column operation. Step1 Row OperationColumn Operation Row Operation Column Operation message alpha message beta Concurrent Schedule This Work : Accelerating Schedule time row 1 col. 1 row 2 col. 2 row 3 col. 3 row 4 col. 4 row 2 col.1-1 row 3row 4 col.1-2col.1-3col.2-1col.2-2col.2-3col.3-1col.3-2col.3-3 The updated message by the row operations are fed into the column operation immediately after the row operations. The number of column operations increases three times compared to the concurrent schedule. The decoding performance depends on the scheduling of the row and column operations.

Waseda University LDPC Decoder Chip Implementation Total Area [μm 2 ] Power [mW] Average #of Iterations Throughput [Mbps] Power/Thr. [mW/Mbps] Bit Error Rate Concurrent Schedule 10,562, Proposed Schedule 11,238, Experimental Results. (TSMC 0.18μm CMOS, SNR=4.5, Iteration CFU1 8 8×3=24 CFUs BFU1 8 8×6=48 BFUs Row Operation Modules.... SRAM for message beta (18 banks) SRAM for initial messages (6 banks).... SRAM for output data (6 banks) SRAM for message alpha (18 banks) Output Module Parity Check Module Input Module Controller Column Operation Modules output data input data Code length3,072 [bits] Code rate0.5, (3,6)-regular Design process0.18um, 6Metal,CMOS Chip size5.0mm* 5.0mm Gate count96,945 (Decoder Core) # of CFU3 * 8 = 24 # of BFU6 * 8 = 48 Total SRAM Area7,113,932 [μm 2 ] PLL Area266,136 [μm 2 ] Chip Density49% Clock Frequency120 [MHz] (Max) Summary of the LDPC Decoder Chip SRAM for message β SRAM for message β LDPC Decoder Core SRAM for message α SRAM for message α