VHDL-AMS Reballoting 1076.1 FDL'03, 9/24/2003 Ernst Christen.

Slides:

Advertisements

Similar presentations

3-13 Alternate Logic-Gate Representations

Advertisements

©2004 Brooks/Cole FIGURES FOR CHAPTER 20 VHDL FOR DIGITAL SYSTEM DESIGN Click the mouse to move to the next page. Use the ESC key to exit this chapter.

VHDL in digital circuit synthesis (tutorial) dr inż. Miron Kłosowski EA 309

VHDL Lecture 1 Megan Peck EECS 443 Spring 08.

CMSC 611: Advanced Computer Architecture

VHDL Refresher ECE 437 April 13, 2015 Motivation ECE 337 is a prerequisite But… –You may have taken 337 a few semesters previous –Breaks causes memory.

Introduction To VHDL for Combinational Logic

Lecture #28 Page 1 ECE 4110– Sequential Logic Design Lecture #28 Agenda 1.Counters Announcements 1.HW #13 assigned 2.Next: Test #2 Review.

Multiplexers Section 3-7 Mano & Kime. Multiplexers & Demultiplexers Multiplexers (Selectors) Lab 1 – Behavioral VHDL -- Multiplexers MUX as a Universal.

GSC /07/2015GSC-8, OTTAWA Ken Biholar T1X1 Chairman Wayne Zeuch T1 Vice Chairman Committee T1 Work on Digital Hierarchies.

Digital Logic with VHDL EE 230 Digital Systems Fall 2006 (10/17/2006)

Electronics’2004, Sozopol, September 23 Design of Mixed Signal Circuits and Systems for Wireless Applications V. LANTSOV, Vladimir State University

CSE 425: Semantic Analysis Semantic Analysis Allows rigorous specification of a program’s meaning –Lets (parts of) programming languages be proven correct.

2-to-1 Multiplexer: if Statement Discussion D2.1 Example 4.

VHDL function CLBM and Inference Presenter: Jie Li Stevens Institute of Technology Sep 2, 2010.

VHDL Quick Start Peter J. Ashenden The University of Adelaide.

VoIP Voice Transmission Over Data Network. What is VoIP?  A method for Taking analog audio signals Turning audio signals into digital data Digital data.

EE 4272Spring, 2003 EE4272: Computer Networks Instructor: Tricia Chigan Dept.: Elec. & Comp. Eng. Spring, 2003.

VHDL Intro What does VHDL stand for? VHSIC Hardware Description Language VHSIC = Very High Speed Integrated Circuit Developed in 1982 by Govt. to standardize.

These courseware materials are to be used in conjunction with Software Engineering: A Practitioner’s Approach, 6/e and are provided with permission by.

VHDL-AMS VHDL-Analog and Mixed Signal Extensions.

1 Data Object Object Types A VHDL object consists of one of the following: –Signal, Which represents interconnection wires that connect component instantiation.

Geog 463: GIS Workshop May 15, 2006 Information Systems Architecture Reading: Zachman 1987.

What is a Protocol A set of definitions and rules defining the method by which data is transferred between two or more entities or systems. The key elements.

IAY 0600 Digital Systems Design

Protocol Architectures. Simple Protocol Architecture Not an actual architecture, but a model for how they work Similar to “pseudocode,” used for teaching.

IAY 0600 Digitaalsüsteemide disain Event-Driven Simulation Alexander Sudnitson Tallinn University of Technology.

Analog and Mixed-Signal Modeling with VHDL-AMS Abdulhadi Shoufan and Sorin Alexander Huss EWME A. Shoufan Slide 1 ISS.

Studio Session 1: Introduction to VHDL and related Tools EE19D – 25/01/2005.

6 Chapter 1 Introduction Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display.

VHDL Project I: Introduction to Testbench Design Matthew Murach Slides Available at:

VHDL FLI. FLI Definition FLI routines are C programming language functions that provide procedural access to information within the HDL simulator.

Introduction to Chapter 3  Now that we understand the concept of binary numbers, we will study ways of describing how systems using binary logic levels.

Fall 2004EE 3563 Digital Systems Design EE 3563 VHSIC Hardware Description Language  Required Reading: –These Slides –VHDL Tutorial  Very High Speed.

William Stallings Data and Computer Communications

Introduction to VLSI Design – Lec01. Chapter 1 Introduction to VLSI Design Lecture # 11 High Desecration Language- Based Design.

Ch.2 Part E: VHDL, SystemC EECE **** Embedded System Design.

Introduction to VHDL Simulation … Synthesis …. The digital design process… Initial specification Block diagram Final product Circuit equations Logic design.

P1801 – Merging of Power Domains Gary Delp. 2 Draft - proposal provided to P1801 (and other groups) by LSI - #include LSI Confidential Purpose Provide.

NETWORKING FUNDAMENTALS. Network+ Guide to Networks, 4e2.

PentiumPro 450GX Chipset Synthesis Steen Larsen Presentation 1 for ECE572 Nov

Digital System Projects

VHDL Discussion Subprograms IAY 0600 Digital Systems Design Alexander Sudnitson Tallinn University of Technology 1.

1 January 25, 2016 P1800 SV Charter Maintain and enhance SystemVerilog language.

IAY 0600 Digital Systems Design Event-Driven Simulation VHDL Discussion Alexander Sudnitson Tallinn University of Technology.

Hardware Description Languages ECE 3450 M. A. Jupina, VU, 2014.

Integration Subcommittee May 26, 2010 Meeting David W. Smith IEEE DASC P Working Group

IAY 0600 Digital Systems Design VHDL discussion Structural style Modular design and hierarchy Part 1 Alexander Sudnitson Tallinn University of Technology.

Lecture and laboratory No. 10 Modeling product as system Óbuda University John von Neumann Faculty of Informatics Institute of Applied Mathematics Master.

Fundamentals of Digital Signal Processing יהודה אפק, נתן אינטרטור אוניברסיטת תל אביב.

SUBJECT : DIGITAL ELECTRONICS CLASS : SEM 3(B) TOPIC : INTRODUCTION OF VHDL.

McGraw-Hill©The McGraw-Hill Companies, Inc., 2000 Lecture 3 : Network Architectures 1.

May 20, 2010 Meeting David W. Smith

Structural style Modular design and hierarchy Part 1

IAY 0600 Digitaalsüsteemide disain

Mixed-Digital/Analog Simulation and Modeling Research

Structural style Modular design and hierarchy Part 1

Grid Metadata Management

Connecting Networks Repeater: physical layer Bridge: data link layer

IAY 0600 Digital Systems Design

Cryptol aided formal verification of VHDL code

Peter J. Ashenden The University of Adelaide

Structural style Modular design and hierarchy Part 1

VHDL Discussion Subprograms

VHDL Introduction.

VHDL Discussion Subprograms

How do you achieve deterministic concurrent simulation.

Business Add-Ins.

Digital Electronics and Logic Circuit

Digital Logic with VHDL

Presentation transcript:

VHDL-AMS Reballoting FDL'03, 9/24/2003 Ernst Christen

© 2003 Synopsys, Inc. (2) Reasons for Reballoting IEEE Std was approved in 1999 IEEE Standards must be reaffirmed every 5 years

© 2003 Synopsys, Inc. (3) Necessary Updates to IEEE Std Synchronization with IEEE Std Correction of errata  8 page errata sheet, published at eda.org/analog Definitional errors (including examples) Typographical errors Layout issues  Several more errata

© 2003 Synopsys, Inc. (4) Enhancements to Consider Postponed requirements  Handling of mixed nets  Support for "analog" and "digital" architecture for an entity Problem is that ports of entity are unchangeable

© 2003 Synopsys, Inc. (5) Mixed Nets A net where participating objects are of different object classes  signal  quantity  terminal Compare with VHDL net where all participating objects are signals  Types may be different

© 2003 Synopsys, Inc. (6) Handling of Mixed Nets Insert conversion model between disparate objects  Conversion model defines semantics of mixed connection Can be arbitrarily complex and include, in addition to value "translation", loading effects, power supply dependency, etc.  Note that signal ports and quantity ports are directional, but terminal ports are not

© 2003 Synopsys, Inc. (7) Mixed Nets: Local Focus Define semantics of a port association element whose formal and actual are of different object class Advantage  Could follow type conversion/conversion function paradigm Disadvantage  Information loss if association elements at different levels of hierarchy are involved

© 2003 Synopsys, Inc. (8) Mixed Nets: Global Focus If mixed net includes a terminal, convert net to a node, otherwise convert net to a quantity net Insert conversion models between the net and the objects connected to the net that have a different object class Advantage  Best approach possible Disadvantage  Multiphase elaboration  Definitional difficulties with conversion fcts

© 2003 Synopsys, Inc. (9) Mixed Nets: Global Focus: Example tt s q t s s

© 2003 Synopsys, Inc. (10) Mixed Nets: Global Focus: Example tt s t q s s conversion models

© 2003 Synopsys, Inc. (11) Mixed Nets: Global Focus: Example tt s t q s s