Redefining the FPGA

SSTL3 1x CLK 2x CLK LVTTL LVCMOS GTL+ Virtex as a System Component 2x CLK SDRAM Backplane Logic Translators Custom Logic Clock Mgmt Old FPGA Glue Logic Old FPGA Cache Memory Processor 100MHz System Performance 1M Gates

Density Leadership XC4085XL XC40125XV Virtex XCV1000 Density (system gates) 10M Gates In 2002 Virtex II Virtex Spans 50K to 1 Million System Gates XC40250XV 10M 2M 1M 250k 180k 500k One million gates available today

Virtex Provides Quantum Leap in FPGA Performance Simple I/O Reg I/O Virtex SelectIO 200MHz 100MHz Virtex 4x Increase in I/O Performance I/O Performance Internal Logic Performance Other FPGAs Performance (MHz) Year

Virtex ClockSync DLLs Allow 200MHz System Performance DLL1 DLL2 DLL3 DLL4 Deskew Clocks on Chip Manage up to 4 System Clocks Deskew Clocks on Board Cascade DLLs Generate Clocks -multiply -divide -shift 4 DLLs in each Virtex Device Convert Clock Levels using SelectI/O Delay Locked Loops Synchronize on-chip and board level clocks

Virtex Supports 17 I/O Standards SDRAM SSTL GTL+ LVTTL LVCMOS CTT SRAM HSTL Chip to Chip LVTTL, LVCMOS, 5VTTL Chip to Memory SSTL2-I, SSTL2-II, SSTL3-I, SSTL3-II, HSTL-I, HSTL-III, HSTL-IV, CTT Chip to Backplane PCI66, PCI33-5V, PCI33 3.3V, GTL, GTL+, AGP Future SelectI/O Technology allows support for future standards Select I/O TM Technology Any standard on any pin Multiple standards simultaneously

200 MHz Memory Continuum bytes kilobytes megabytes Virtex On-Chip SelectRAM+ TM Memory 16x1 4Kx1 2Kx2 1Kx4 512x8 256x16 DSP Coefficients Small FIFOs Shallow/Wide Large FIFOs Packet Buffers Video Line Buffers Cache Tag Memory Deep/Wide SDRAM ZBT SSRAM SGRAM 3 Level Memory Hierarchy Enables 200MHz Bandwidth Highest performance FPGA memory system Distributed RAMBlock RAMExternal RAM

Virtex Software Breaks New Ground  The Industry’s two million gate design capabilities  Highest performance through push button flows  Web enabled design tools (Silicon Xpresso)  SmartIP TM Technology for high design productivity Available Today in v2.1i!

SmartIP™ Optimized Vector-Based Interconnect  Predictable high performance  Optimized for synthesis 2ns DSP 2ns ATM 66MHz PCI

 Industry’s first Web-enabled design solutions  Industry’s fastest compilation times  Industry’s highest performance  Industry's best support for High-Level design flows HDL design Design re-use / Cores Robust functional and timing verification  Industry’s first 2 Million Gate FPGA  Industry’s only “Real PCI” design Virtex Software Breaks New Ground

25% 50% 100% A History of 2x Runtime Improvements For a given design size, runtimes have been cut in half with the release of each new version of Xilinx Development Systems. v1.3 v1.4 v1.5i v2.1i 12% Runtime Software Release v2.1i compiles 8x FASTER than v1.3 ! 4X 2X 8X 1X

Available now 1 Dynamic Const Coeff. Multiplier 1 Divider 2 Block Memory modules 3 Gate modules 4 Multiplexer functions 2 Registers, FF and latch based 1 Parallel Multiplier 1 Sine/cosine LUT 2 Distributed Memories 1 Adder/Subtractor 1 Accumulator 1 Comparator 1 Binary Counter 1 Asynch FIFO (FAE Release) End of December 1 Asynch FIFO 1 Binary Decoder 1 Two's Complement 2 Shift Register RAM/FF 1 FIR Filter (Pre-release now, Dec-99) 3 FFTs (Pre-release now; Dec-99) 1 NCO (Dec-99) 2 Reed Solomon (Pre-release now, 1Q00) PCI32/33 (XCV300 now) PCI64/33/66 (XCV300, XCV1000 now) 36 by Dec Virtex Series LogiCOREs DSP Cores BaseBLOX/General-purpose PCI Cores BaseBLOX/General-purpose $ $ $

Xilinx PCI Device Support  Virtex and Virtex-E support now PCI32/33 in XCV300/E-6 BG432 PCI64/66/33 in XCV300/E-6 BG432 and XCV1000/E-6 FG680 Virtex support 5 V and 3.3 V PCI Virtex-E supports 3.3 V PCI  Full 33 MHz compliance in additional Virtex and Virtex-E devices Achieved using Re-Targeting Guide (RT-Guide)

Existing Virtex AllianceCOREs * *As of Dec Bus Interfaces I 2 C Generic bus arbiter Communications DVB satellite modulator 10/100 Ethernet MAC DES Engine HDLC Controller (2 partners) Reed Solomon encoder (2 partners) Reed Solomon decoder (2 partners) UTOPIA slave interface (2 partners) Convolutional encoder Viterbi Decoder (2 partners) ADPCM Channel noise model Distributed Sample Scrambler and Descrambler Processor Peripherals Compact UART A A SDRAM Controller (2 types) Processors 8051 DSP functions YUV2RGB color space converter RGB2YUV color space converter

Density Range and Package Leadership

Industry Leading Price Points End of 1999 pricing based on 100,000 units * 6,000 gates per dollar

Virtex Testimonials AdTech, Inc. "These million gate devices enable our test modules to provide thousands of continuous measurements at telecom speeds up to 2.4 gigabits per second," said Carl Uyehara, vice president of engineering at Adtech, Inc., a leading supplier of broadband test systems. "We especially like the fact that Virtex devices are programmable. This allows us to use a single test module for multiple transmission technologies such as ATM and frame relay, which provides huge cost savings and convenience for our customers plus future enhancement capability.” Carl Uyehara, vice president of Engineering Hughes Space and Communication Company "The critical features of Virtex, such as the segmented routing and 0.22 micron feature size, allowed new levels of performance for our high-speed digital designs. The lower voltage and higher performance logic of the Virtex process are unmatched from any other supplier. The level of support from the design development and the hotline assistance that Xilinx offered with the new family also impressed us.” Ted Pascaru, Senior Staff Engineer News Data Services (NDS) "Virtex FPGAs have allowed us to implement our next generation digital TV broadcast systems in record time. A key time saver was the availability of multiple DLLs that allowed us to synchronize a 74 MHz clock to more than 30 devices including multiple FPGAs, SDRAMs, and other components. Designing a no-skew clock system from scratch would take months. Xilinx delivered a ready-made solution to us with Virtex FPGAs.” John Simmons, Project Manager Nortel Networks "In our next generation networking product, we specifically needed block RAM with true dual-port capabilities. We investigated various programmable solutions available and found that no other vendor could provide a single chip solution containing block memory with the ability to read and write to one port and simultaneously read from the other. Additionally, the Virtex DLLs performance was required in order to interface directly to an ASIC running at 78 MHz. Not only do Virtex devices meet our 78 MHz internal performance requirements, they meet our external interface performance requirements by providing very fast 'clock-to-out' timing on even the slowest device.” Ranvir Chitkara, Director of Engineering

Summary  Complete Virtex solution available NOW Silicon, Software, Cores, Support  Breaks density and performance barriers 1M Gates, 200 MHz Chip to Chip performance  The Only System Level FPGA solution Timing, Memory, Interface and Integration  Available at industry leading price points Virtex moves FPGAs from glue to system component