B => J/     Gerd J. Kunde PHENIX Silicon Endcap  Mini-strips (50um*2mm – 50um*11mm)  Will not use ALICE chip  Instead custom design based on FPIX and SVX4 components from FNAL for mini-strips  Current discussions on ‘data-pushing’ vs. ‘pipeline’ architecture  Met with Yarema group at FEE2003  Developed concept for data-push and displaced-vertex trigger  Started collaborative effort with University Heidelberg LOGO !!!!!!

B => J/     Gerd J. Kunde Si Lampshade Layout  50 mu radial pitch (z vertex reconstruction)  3000 “mini-strips”  3.5 cm < r < 18.5 cm  128 “towers” in phi  mini-strips from 2.2 mm to 11.6 mm  2 rows of strips in one “dual-tower”  16 dual-towers in “wedge”  8 wedges in one “lampshade”  8 lampshades ( ~ 20 degree tilt) r = 3.5 cm r = 18.5 cm Preliminary 6/03

B => J/     Gerd J. Kunde FPIX2 Features Advanced mixed analog/digital design 128 rows x 22 columns (2816 channels) 50 µm x 400 µm pixels High speed readout intended for use in Level 1 trigger. Up to 840 Mbits/sec data output. Very low noise Excellent threshold matching DC coupled input Fully programmable device

B => J/     Gerd J. Kunde FPIX2 Status Produced 3168 chips in engineering run Minor tweaking of design needed before production Mixed analog/digital design has excellent performance with insignificant interference and cross talk. Chip size is 8.96 mm x 10.2 mm (91 mm 2 ) Yield is high Chip and readout can be used “as is” in other pixel applications First flip-chip assemblies this week Could start comparative testing ……

B => J/     Gerd J. Kunde Components for Phenix Chip PHX Use modified FPIX2 front end Use relaxed bump bonding connections Either data-push from FPIX or pipeline from SVX Use backside contact for ground return (as done in SVX4) Use slow programming control from FPIX2 May use modified output drivers from FPIX2

B => J/     Gerd J. Kunde Layout Diagram for PHX Chip Bump bonds Programming interface 1 st and 2 nd stage and discriminator Pipeline Digital interface Complete bus on chip

B => J/     Gerd J. Kunde PHX Chip Layout: 2 columns 256 channels/column 3.8 mm x 13 mm = 49.4 mm 2 Bump bonds on 200 um pitch 50 µm dia bumps 512 bumps plus inter-chip bumps FPIX2 Layout for comparison: Chip area = 91 mm 2 Bump bonds on 50 µm pitch 12 µm dia bumps 2816 bumps signals & power

B => J/     Gerd J. Kunde PHX: Tower Section Ray Yarema, FNAL, June 9th Carbon Fiber Support and Cooling

B => J/     Gerd J. Kunde Wedge Assembly/ Data Interface 16 wedges/lampshade: receiver for data-push fiber optics to DAQ One wedge Uni Heidelberg 2.5 Gigabit fiber

B => J/     Gerd J. Kunde PHX Schedule Design specifications completed 10/03 Start design 12/03 Submit prototype 7/04 Prototype testing completed 12/04 Redesign completed for engineering run 1/05 Engineering run back 3/05 Ray Yarema, FNAL, June 9th

B => J/     Gerd J. Kunde PHX Cost Chip design/testing – 2 man-years - $275K (includes all overhead costs) Prototype chip fabrication- $40K (small chip) Test board $5K Engineering run (10-12 wafers) $200K 9 Extra wafers using same masks - $45K Production wafer level testing –engineering, tech time, circuit board, probe card - $60K Contingency tbd Ray Yarema, FNAL, June 9th 20 wafers total

B => J/     Gerd J. Kunde Trigger on displaced b-vertices ctau ~ 500 mu Started new collaboration with V.Lindenstruth from University Heidelberg –UH designed a displaced vertex trigger for LHCb –UH designed a tracklet processor for ALICE –Has chip to provide LVDS to fiber interface 2.5 Gbit/s Trigger would require –Data-push technology –Barrel and Endcap with same readout technology Trigger tracking software from LHCb project

B => J/     Gerd J. Kunde Endcap Summary Mini-strips on wedges Readout via PHX from Fermilab Same chips for barrel ?! –FPIX for layer 1,2 (two pixel layers !!!) Displaced vertex tracking with 10% occupancy gives too many ghosts, see layout of all LHC trackers –PHX for layer 3,4 (mini- strips) Trigger on displaced vertices ??? !!!!!!!! –We should start collaboration wide discussion on ‘triggers in the upgrade era’